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Encyclopedia > Silicon on insulator

Silicon on insulator technology (SOI) refers to the use of a layered silicon-insulator-silicon substrate in place of conventional silicon substrates in semiconductor manufacturing, especially microelectronics, to reduce parasitic device capacitance and thereby improve performance.[1] SOI-based devices differ from conventional silicon-built devices in that the silicon junction is above an electrical insulator, typically silicon dioxide or (less commonly) sapphire. The choice of insulator depends largely on intended application, with sapphire being used for radiation-sensitive applications and silicon oxide preferred for improved performance and diminished short channel effects in microelectronics devices [2]. The insulating layer and topmost silicon layer also vary widely with application. The first implementation of SOI was announced by IBM in August 1998.[3] Look up substrate in Wiktionary, the free dictionary. ... For other uses, see Sapphire (disambiguation). ...

Contents

Industry need

The implementation of SOI technology is one of several manufacturing strategies employed to allow the continued miniaturization of microelectronic devices, colloquially referred to as extending Moore's Law. Reported benefits of SOI technology relative to conventional silicon (bulk CMOS) processing include: Gordon Moores original graph from 1965 Growth of transistor counts for Intel processors (dots) and Moores Law (upper line=18 months; lower line=24 months) For the observation regarding information retrieval, see Mooers Law. ... For other uses, see CMOS (disambiguation). ...

  • Lower parasitic capacitance due to isolation from the bulk silicon, which improves power consumption at matched performance.
  • Resistance to latchup due to complete isolation of the n- and p- well structures.

From a manufacturing perspective, SOI substrates are compatible with most conventional fab processes. In general, an SOI-based process may be implemented without special equipment or significant retooling of an existing factory. Among challenges unique to SOI are novel metrology requirements to account for the buried oxide layer and concerns about differential stress in the topmost silicon layer. The primary barrier to SOI implementation is the drastic increase in substrate cost, which contributes an estimated 10 - 15% increase to total manufacturing costs.[4] A latchup is the inadvertent creation of a low-impedance path between the power supply rails of an electronic component, triggering a parasitic structure, which then acts as a short circuit, disrupting proper functioning of the part and possibly even leading to its destruction due to overcurrent. ...


Manufacture of SOI wafers

SiO2-based SOI wafers can be produced by several methods:

SIMOX process
SIMOX process
  • Wafer Bonding[8] [9] - the insulating layer is formed by directly bonding oxidized silicon with a second substrate. The majority of the second substrate is subsequently removed, the remnants forming the topmost Si layer.
    • One prominent example of a wafer bonding process is the Smart Cut™ method developed by the French firm Soitec which uses ion implantation followed by controlled exfoliation to determine the thickness of the uppermost silicon layer.
    • NanoCleave™ is a technology developed by Silicon Genesis Corporation that separates the silicon via stress at the interface of silicon and silicon-germanium alloy.[10]
    • ELTRAN™ is a technology developed by Canon which is based on porous silicon and water cut.[11]
  • Seed methods[12] - wherein the topmost Si layer is grown directly on the insulator. Seed methods require some sort of template for homoepitaxy, which may be achieved by chemical treatment of the insulator, an appropriately oriented crystalline insulator, or vias through the insulator from the underlying substrate.

An exhaustive review of these various manufacturing processes may be found in reference [1] Ion implantation is a materials engineering process by which ions of a material can be implanted into another solid, thereby changing the physical properties of the solid. ... Ion implantation is a materials engineering process by which ions of a material can be implanted into another solid, thereby changing the physical properties of the solid. ... Smart Cut is a silicon on insulator (SOI) technology developed by SOITEC, consisting in a materials engineering process used in the semiconductor industry. ... Soitec is a French semiconductor manufacturer which is specialised in the production of Silicon-On-Insulator (SOI) wafers. ...

Smart Cut process
Smart Cut process

Use in the microelectronics industry

IBM began to use SOI in high end RS64-IV Istar PowerPC processors in 2000. Other examples of microprocessors built on SOI technology include AMD's 130 nm, 90 nm and 65 nm single, dual and quad core processors since 2001.[13] Freescale adopted SOI in their PowerPC 7455 CPU in late 2001, currently Freescale is shipping SOI products in 180nm, 130nm, 90nm and 65nm lines.[14] The 90 nm Power Architecture based processors used in the Xbox 360, PlayStation 3 and Wii use SOI technology as well. Competitive offerings from Intel, however, such as the 65 nm Core 2 and Core 2 Duo microprocessors, are built using conventional bulk CMOS technology. Intel's new 45 nm process will continue to use conventional technology. However, Intel made a claim of single-chip silicon laser based on SOI.[15] For other uses, see IBM (disambiguation) and Big Blue. ... The IBM RS64 family of processors is used in the RS/6000 and AS/400 server product lines. ... Advanced Micro Devices, Inc. ... American corporation Freescale Semiconductor, Inc. ... PowerPC is a RISC microprocessor architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ... The Power Architecture logo Power Architecture is a broad term to describe similar instruction sets for RISC microprocessors developed and manufactured by such companies as IBM, Freescale, AMCC, Tundra and P.A. Semi. ... It has been suggested that Xbox 360 Elite be merged into this article or section. ... The PlayStation 3 , trademarked PLAYSTATION®3,[3] commonly abbreviated PS3) is the third home video game console produced by Sony Computer Entertainment; successor to the PlayStation 2. ... The Wii (pronounced as the pronoun we, IPA: ) is the fifth home video game console released by Nintendo. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... Core 2 Duo brand logo This article is about Intel processors branded as Intel Core 2. ... Core 2 Duo brand logo Core 2 Extreme brand logo Core 2 is an eighth-generation x86 architecture microprocessor produced by Intel based on an all-new CPU architecture called the Intel Core Microarchitecture, which is the successor of NetBurst microarchitecture that has powered most Intel processors since 2000. ... For other uses, see CMOS (disambiguation). ...


On the foundry side, TSMC claimed no customer wanted SOI.[16] But Chartered Semiconductor devoted a whole fab to SOI.[17] Taiwan Semiconductor Manufacturing Company, Limited (Traditional Chinese: 台灣積體電路製造股份有限公司, abbrev. ... Chartered Semiconductor Manufacturing SGX: C27 NASDAQ: CHRT (abbreviated CSM) is the worlds fourth largest dedicated independent semiconductor foundry, with its headquarters and main operations located in the Woodlands Industrial Park, Kranji Singapore. ...


References

  1. ^ a b Celler, G.K., Cristoloveanu, S. J App Phys, 93, 4955 (2003)
  2. ^ SOI design: analog, memory and digital techniques by Andrew Marshall & Sreedhar Natarajan
  3. ^ IBM Advances Chip Technology With Breakthrough For Making Faster, More Efficient Semiconductors
  4. ^ IBM touts chipmaking technology
  5. ^ http://www.google.com/patents?vid=5888297
  6. ^ http://www.google.com/patents?vid=USPAT5061642
  7. ^ SIMOX-SOI Technology: Ibis Technology
  8. ^ "SemiConductor Wafer Bonding: Science and Technology" by Q.-Y. Tong & U. Gösele, Wiley-Interscience, 1998, ISBN:978-0471574811
  9. ^ http://www.google.com/patents?vid=4771016
  10. ^ http://www.sigen.com/
  11. ^ JSAPI_vol.4
  12. ^ http://www.google.com/patents?q=5417180&btnG=Search+Patents
  13. ^ Chip Architect: Intel and Motorola/AMD's 130 nm processes to be revealed
  14. ^ Process Technology
  15. ^ http://www.eetasia.com/ART_8800359617_499481,499482.HTM
  16. ^ TSMC has no customer demand for SOI technology - Fabtech - The online information source for semiconductor professionals
  17. ^ CHARTERED EXPANDS FOUNDRY MARKET ACCESS TO IBM's 90nm SOI TECHNOLOGY

External links

  • AMDboard - a site with extensive information regarding SOI technology
  • Advanced Substrate News - a newsletter about the SOI industry, produced by Soitec.
  • MIGAS'04 - The 7th session of MIGAS International Summer School on Advanced Microelectronics, devoted to SOI technology and devices.

  Results from FactBites:
 
Silicon-on-insulator optical waveguide Michelson interferometer sensor for temperature monitoring - Patent 6603559 (2127 words)
Silicon is very easy to acquire and very cheap, and has been the major material in the IC manufacturing process, so the present invention uses silicon-on-insulator as the substrate.
Silicon-on-insulator waveguide Bragg grating 2 comprises an amorphous silicon layer 21, a sinusoidal silicon grating layer 22, a silicon dioxide insulating layer 16 and a silicon substrate 17, as shown in FIG.
By the couple-mode equation, the present invention designed an optimal silicon-on-insulator waveguide Bragg grating having waveguide width 11 of 6.mu.m, sinusoidal silicon grating layer 22 of 1.5.mu.m, grating period 23 of 0.2215.mu.m, grating length 24 of 100.mu.m, silicon dioxide insulation layer 16 of 0.4.mu.m, and amorphous silicon layer 21 of 1.mu.m.
Silicon on insulator - Wikipedia, the free encyclopedia (425 words)
Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of silicon dioxide(SiO
The advantage is that this insulator reduces the capacitance, meaning the transistor has less to charge-up before completing a switch, which results in reduced switching time.
The thin layer of silicon that is left behind is isolated from the substrate by what was originally the surface oxide layers.
  More results at FactBites »

 
 

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