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Encyclopedia > SSE3

SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU. In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs. The earlier SIMD instruction sets on the x86 platform, from oldest to newest, are MMX, 3DNow! (developed by AMD), SSE and SSE2. The following article is about the multinational corporation; intel is also an abbreviation for intelligence, used in reference to military intelligence and espionage. ... SSE (Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel, and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... IA-32, sometimes generically called x86-32, is the computer architecture of Intels most successful microprocessors. ... Pentium 4 (with hyper-threading) brand logo The Pentium 4 is a seventh-generation x86 architecture microprocessor produced by Intel and is their first all-new CPU design, called the NetBurst architecture, since the Pentium Pro of 1995. ... Advanced Micro Devices, Inc. ... The Athlon 64 (codenamed ClawHammer, Newcastle, Winchester, Venice, and San Diego) represents AMDs entry into the consumer 64-bit microprocessor market, released on September 23, 2003. ... -1... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... MMX is a SIMD instruction set designed by Intel, introduced in their Pentium MMX microprocessors. ... The first 3DNow! CPU 3DNow! is the name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. ... SSE (Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel, and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2 is one of the IA-32 SIMD instruction sets, first introduced by Intel with the initial version of the Pentium 4 in 2001. ...

Contents


Changes

The most notable change is the capability to work horizontally in a register, as opposed to the more or less strictly vertical operation of all previous SSE instructions. More specifically, instructions to add and subtract the multiple values stored within a single register have been added. These instructions simplify the implementation of a number of DSP and 3D operations. There is also a new instruction to convert floating point values to integers without having to change the global rounding mode, thus avoiding costly pipeline stalls. Finally, the extension adds LDDQU, an alternative misaligned integer vector load that has better performance on Netburst architectures for loads that cross cacheline boundaries. Digital signal processing (DSP) is the study of signals in a digital representation and the processing methods of these signals. ... To meet Wikipedias quality standards, this article or section may require cleanup. ... The NetBurst Microarchitecture is the name given to the new architecture that succeded the P6 microarchitecture in the x86 family of CPUs made by Intel. ...


CPUs with SSE3

Advanced Micro Devices, Inc. ... The Athlon 64 (codenamed ClawHammer, Newcastle, Winchester, Venice, and San Diego) represents AMDs entry into the consumer 64-bit microprocessor market, released on September 23, 2003. ... Athlon 64 X2 Logo Athlon 64 X2 E6 3800+ The Athlon 64 X2 is the first dual-core desktop CPU manufactured by AMD. It is essentially a processor consisting of two Athlon 64 cores joined together on one die with some additional control logic. ... The Athlon 64 (codenamed ClawHammer, Newcastle, Winchester, Venice, and San Diego) represents AMDs entry into the consumer 64-bit microprocessor market, released on September 23, 2003. ... The AMD Opteron is the first eighth-generation x86 processor (K8 core), and the first of AMDs AMD64 (x86-64) processors, released April 22, 2003. ... Sempron 3000+ Sempron is AMDs newest low-end CPU, replacing the Duron processor and competing against Intels Celeron D processor. ... Turion 64 Logo Turion 64 is AMDs 64-bit mobile processor, intended to compete with Intels Pentium M. It is compatible with AMDs Socket 754 and is equipped with 512 or 1024 KB of L2 cache, a 64-bit single channel on-die memory controller, and an... The following article is about the multinational corporation; intel is also an abbreviation for intelligence, used in reference to military intelligence and espionage. ... 633MHz Celeron A Celeron is any of a large number of different budget x86 microprocessors produced by Intel and marketed as a second line to complement their more expensive but higher-performance Pentium CPUs. ... Pentium 4 (with hyper-threading) brand logo The Pentium 4 is a seventh-generation x86 architecture microprocessor produced by Intel and is their first all-new CPU design, called the NetBurst architecture, since the Pentium Pro of 1995. ... Introduced in March 2003, the Pentium M is an x86 architecture microprocessor designed and manufactured by Intel. ... VIA Technologies is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory, and is part of the Formosa Plastics Group. ... This article needs to be cleaned up to conform to a higher standard of quality. ... The VIA C3 is an x86 central processing unit for personal computers. ...

New Instructions

Common Instructions

Arithmetic

  • ADDSUBPD - ( Add-Subtract-Packed-Double )
    • Input - { A0, A1 }, { B0, B1 }
    • Output - { A0 - B0, A1 + B1 }
  • ADDSUBPS - ( Add-Subtract-Packed-Single )
    • Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
    • Output: { A0 - B0, A1 + B1, A2 - B2, A3 + B3 }

AOS ( Array Of Structures )

  • HADDPD - ( Horizontal-Add-Packed-Double )
    • Input: { A0, A1 }, { B0, B1 }
    • Output: { B0 + B1, A0 + A1 }
  • HADDPS ( Horizontal-Add-Packed-Single )
    • Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
    • Output: { B0 + B1, B2 + B3, A0 + A1, A2 + A3 }
  • HSUBPD - ( Horizontal-Subtract-Packed-Double )
    • Input: { A0, A1 }, { B0, B1 }
    • Output: { A0 - A1, B0 - B1 }
  • HSUBPS - ( Horizontal-Subtract-Packed-Single )
    • Input: { A0, A1, A2, A3 }, { B0, B1, B2, B3 }
    • Output: { A0 - A1, A2 - A3, B0 - B1, B2 - B3 }
  • LDDQU - As stated above, this is an alternative misaligned integer vector load. It can be helpful for video compression tasks.
  • MOVDDUP, MOVSHDUP, MOVSLDUP - These are also used for complex numbers, and can be helpful for wave calculation like sound.
  • FISTTP - Like the older x87 FISTP instruction, but ignores the floating point control register's rounding mode settings and uses the "chop" (truncate) mode instead. Allows omission of the expensive loading and re-loading of the control register in languages such as C where float-to-int conversion requires truncate behaviour by standard.

Intel Instructions

  • MONITOR, MWAIT - These optimize multi-threaded applications, giving processors with Hyper-Threading better performance.

Source: X-bit Labs
Explanation of Terms Hyper-Threading (HTT = Hyper Threading Technology) is Intels trademark for their implementation of the simultaneous multithreading technology on the Pentium 4 microarchitecture. ... The subject of computer numbering formats has to do with the various methods implemented in computer and calculator circuits for these machines to represent digits and numbers. ...


If you want to get more detailed information, go to The SSE3 Overview by Intel (tm).


  Results from FactBites:
 
Reference.com/Encyclopedia/SSE3 (504 words)
SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture.
Intel introduced SSE3 in early 2004 with the Prescott revision of their Pentium 4 CPU.
In April 2005, AMD introduced a subset of SSE3 in revision E (Venice and San Diego) of their Athlon 64 CPUs.
ChipGeek Features: Intel's upcoming SSE3 extensions (3837 words)
SSE3 looks like it will extend the current SIMD functions for single- or double-precision floating point variables (32 bits or 64 bits).
SSE3 could also provide a mechanism to access FPU functionality without using the FPU's stack (one of the most confusing creations every given the x86/x87 architecture, especially to newbies).
If SSE3 could incorporate an ability to access the FPU functionality without storing results on the FPU stack or register space then that would be a tremendous step forward in computing.
  More results at FactBites »

 
 

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