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Encyclopedia > SSE2

SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. SSE2 was first introduced by Intel with the initial version of the Pentium 4 in 2001. It extends the earlier SSE instruction set, and is intended to fully supplant MMX. Intel extended SSE2 to create SSE3 in 2004. SSE2 added 144 new instructions to SSE, which has 70 instructions. Rival chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of AMD64 64-bit CPUs in 2003. It has been suggested that this article or section be merged with X86 assembly language. ... -1... An instruction set is (a list of) all instructions, and all their variations, that a processor can execute. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The Pentium 4[1] brand refers to Intels mainstream desktop and mobile single-core CPUs (introduced on November 20, 2000[2]) with the seventh-generation NetBurst architecture, which was the companys first all-new design since the Intel P6 of the Pentium Pro branded CPUs of 1995. ... Year 2001 (MMI) was a common year starting on Monday (link displays the 2001 Gregorian calendar). ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. ... Year 2004 (MMIV) was a leap year starting on Thursday of the Gregorian calendar. ... Advanced Micro Devices, Inc. ... The Opteron is AMDs x86 server processor line, and was the first processor to implement the AMD64 instruction set architecture (known generically as x86-64). ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... Year 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ...

Contents

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SSE2 extends MMX instructions to operate on XMM registers, allowing the programmer to completely avoid the eight 64-bit MMX registers "aliased" on the original IA-32 floating point register stack. This permits mixing integer SIMD and scalar floating point operations without the mode switching required between MMX and x87 floating point operations. However, this is overshadowed by the value of being able to perform MMX operations on the wider SSE registers. Referrs to math-related instruction subset of Intel X86 family line of processors. ...


Other SSE2 extensions include a set of cache-control instructions intended primarily to minimize cache pollution when processing indefinite streams of information, and a sophisticated complement of numeric format conversion instructions. Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ... Cache pollution describes situations where an executing computer program loads data into CPU cache unnecessarily, thus causing other needed data to be evicted from the cache into lower levels of the memory hierarchy, potentially all the way down to main memory. ...


AMD's implementation of SSE2 on the AMD64 (x86-64) platform includes an additional 8 registers, doubling the total number to 16 (XMM0 through XMM15). These additional registers are only visible when running in 64-bit mode. Intel adopted these additional registers as part of their support for x86-64 architecture (or in Intel's parlance, "Intel 64") in 2004. The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ...


Differences between x87 FPU and SSE2

The FPU (x87) instructions always store intermediate results with 80-bits of precision. When legacy FPU software algorithms are ported to SSE2, certain combinations of math operations or input datasets can result in measurable numerical deviation. This is of critical importance to scientific computations, if the calculation results must be compared against results generated from a different machine architecture.


A notable problem occurs when a compiler must interpret a mathematical expression consisting of several operations (adding, subtracting, dividing, multiplying). Depending on the compiler (and optimizations) used, different intermediate results of a given mathematical expression may need to be temporarily saved, and later reloaded. This results in a truncation from 80-bits to 64-bits in the x87 FPU. Depending on when this truncation is executed, the final numerical result may end up different. The following Fortran code compiled with G95 is offered as an example.

 program hi real a,b,c,d real x,y,z a=.013 b=.027 c=.0937 d=.79 y=-a/b + (a/b+c)*EXP(d) print *,y z=(-a)/b + (a/b+c)*EXP(d) print *,z x=y-z print *,x end 

Compiling to 387 floating point instructions and running yields:

 # g95 -o hi -mfpmath=387 -fzero -ftrace=full -fsloppy-char hi.for # ./hi 0.78587145 0.7858714 5.9604645E-8 

Compiling to SSE2 instructions and running yields:

 # g95 -o hi -mfpmath=sse -msse2 -fzero -ftrace=full -fsloppy-char hi.for # ./hi 0.78587145 0.78587145 0. 

Differences between MMX and SSE2

SSE2 extends MMX instructions to operate to XMM registers. Therefore, it is possible to convert all existing MMX code to SSE2 equivalent. Since an XMM register is two times as long as an MMX register, loop counters and memory access may need to be changed to accommodate this.


Although one SSE2 instruction can operate on twice as much data as an MMX instruction, performance might not increase significantly. Two major reasons are: accessing SSE2 data in memory not aligned to a 16-byte boundary will incur significant penalty, and the throughput of SSE2 instructions in most x86 implementations is usually smaller than MMX instructions. Intel has recently addressed the first problem by adding an instruction in SSE3 to reduce the overhead of accessing unaligned data, and the last problem by widening the execution engine in their Core microarchitecture. In communication networks, throughput is the amount of digital data per time unit that is delivered over a physical or logical link, or that is passing through a certain network node. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. ... The Intel Core microarchitecture (previously known as the Intel Next-Generation Micro-Architecture, or NGMA) is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. ...


Compiler usage

When first introduced in 2000, SSE2 was not supported by software development tools. For example, to use SSE2 in a Microsoft Developer Studio project, the programmer had to either manually write inline-assembly or import object-code from an external source. Later the Visual C++ Processor Pack added SSE2 support to Visual C++ and MASM Microsoft Visual Studio is Microsofts flagship software development product for computer programmers. ...


The Intel C++ Compiler can automatically generate SSE4/SSSE3/SSE3/SSE2 and/or SSE-code without the use of hand-coded assembly, letting programmers focus on algorithmic development instead of assembly-level implementation. Since its introduction, the Intel C Compiler has greatly increased adoption of SSE2 in Windows application development. Intel C++ Compiler (also known as icc or icl) describes a group of C/C++ compilers from Intel. ...


Since GCC 3, GCC can automatically generate SSE/SSE2 scalar code when the target supports those instructions. Automatic vectorization for SSE/SSE2 has been added since GCC 4. The GNU Compiler Collection (usually shortened to GCC) is a set of programming language compilers produced by the GNU Project. ... Automatic vectorization, in the context of a computer program, refers to the transformation of a series of operations performed linearly, one step at a time, to operations performed in parallel, several at once, in a manner suitable for processing by a vector processor. ...


The Sun Studio Compiler Suite can also generate SSE2 instructions when the compiler flag -xvector=simd is used. The Sun Studio compiler suite is Sun Microsystems flagship software development product for Solaris and Linux. ...


CPUs supporting SSE2

The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... This does not cite any references or sources. ... For other uses, see Turion. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The Intel NetBurst Microarchitecture, called P68 inside Intel, was the successor to the P6 microarchitecture in the x86 family of CPUs made by Intel. ... The Pentium 4[1] brand refers to Intels mainstream desktop and mobile single-core CPUs (introduced on November 20, 2000[2]) with the seventh-generation NetBurst architecture, which was the companys first all-new design since the Intel P6 of the Pentium Pro branded CPUs of 1995. ... This article is about the Intel microprocessor. ... The Celeron brand refers to a range of Intels x86 CPUs for budget/value personal computers. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... Introduced in March 2003, the Pentium M is an x86 architecture microprocessor designed and manufactured by Intel. ... 633MHz Celeron A Celeron is any of a large number of different budget x86 microprocessors produced by Intel and marketed as a budget/value CPU line. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... 633MHz Celeron A Celeron is any of a large number of different budget x86 microprocessors produced by Intel and marketed as a second line to complement their more expensive but higher-performance Pentium CPUs. ... This article is about the Intel mobile processor family. ... The Core 2 brand refers to a range of Intels consumer 64-bit dual-core and MCM quad-core CPUs with the x86-64 instruction set, and based on the Intel Core microarchitecture, which derived from the 32-bit dual-core Yonah laptop processor. ... Transmeta NASDAQ: TMTA develops computing technologies with a focus on reducing power consumption in electronic devices. ... The Efficeon processor is Transmetas second-generation 256-bit VLIW design which employs a software engine to convert code written for x86 processors to the native instruction set of the chip (Code Morphing Software, aka CMS). ... VIA Technologies logo VIA Technologies is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory, and is part of the Formosa Plastics Group. ... VIA C7 Logo The VIA C7 is an x86 central processing unit for personal computers designed by Centaur Technology and sold by VIA Technologies. ...

Notable IA-32 CPUs not supporting SSE2

SSE2 is an extension of the IA-32 architecture. Therefore any architecture that does not support IA-32 does not support SSE2. x86-64 CPUs all implement IA-32, by definition. All known x86-64 CPUs also implement SSE2. Since IA-32 predates SSE2, early IA-32 CPUs did not implement it. SSE2 and the other SIMD instruction sets were intended primarily to improve CPU support for realtime graphics, notably gaming. A CPU that is not marketed for this purpose or that has an alternative SIMD instruction set has no need for SSE2. It has been suggested that this article or section be merged with X86 assembly language. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... It has been suggested that this article or section be merged with X86 assembly language. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ...


The following is a list of CPUs that implemented IA-32 after SSE2 was developed, but that did not implement SSE2:

Advanced Micro Devices, Inc. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... Socket A (also known as Socket 462) is the CPU socket used for AMD flagship processors ranging from the Athlon K7 to the Athlon XP 3200+, and AMD budget processors including the Duron and Sempron. ... This does not cite any references or sources. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The Pentium 4[1] brand refers to Intels mainstream desktop and mobile single-core CPUs (introduced on November 20, 2000[2]) with the seventh-generation NetBurst architecture, which was the companys first all-new design since the Intel P6 of the Pentium Pro branded CPUs of 1995. ... VIA Technologies logo VIA Technologies is a Taiwanese manufacturer of integrated circuits, mainly motherboard chipsets, CPUs, and memory, and is part of the Formosa Plastics Group. ... The VIA C3 is an x86 central processing unit for personal computers produced by VIA Technologies. ... Transmeta NASDAQ: TMTA develops computing technologies with a focus on reducing power consumption in electronic devices. ... Crusoe is a family of x86-compatible microprocessors from Transmeta. ...

See also


  Results from FactBites:
 
SSE2: Information from Answers.com (807 words)
SSE2, Streaming "Single Instruction, Multiple Data" Extensions 2, is one of the IA-32 SIMD instruction sets, first introduced by Intel with the initial version of the Pentium 4 in 2001.
Rival chip-maker AMD added support for SSE2 with the introduction of their Opteron and Athlon 64 ranges of 64-bit CPUs in 2003, and in 2005 added support for the SSE3 instruction set with an updated "E" revision of their processors.
Two major reasons are: accessing SSE2 data in memory not aligned to a 16-byte boundary will incur significant penalty, and the throughput of SSE2 instructions in most x86 implementations is usually smaller than MMX instructions.
  More results at FactBites »

 
 

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