FACTOID # 4: Just 1% of the houses in Nevada were built before 1939.
 
 Home   Encyclopedia   Statistics   States A-Z   Flags   Maps   FAQ   About 
 
WHAT'S NEW
RELATED ARTICLES
People who viewed "SPARC" also viewed:
 

SEARCH ALL

FACTS & STATISTICS    Advanced view

Search encyclopedia, statistics and forums:

 

 

(* = Graphable)

 

 


Encyclopedia > SPARC
Sun UltraSPARC II Microprocessor
Sun UltraSPARC II Microprocessor
Sun UltraSPARC T1 (Niagara 8 Core)

SPARC (Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. Image File history File links Description: Sun UltraSPARCII Microprocessor Source: http://www. ... Image File history File links Description: Sun UltraSPARCII Microprocessor Source: http://www. ... Image File history File links Sun_UltraSPARC_T1. ... Image File history File links Sun_UltraSPARC_T1. ... The reduced instruction set computer, or RISC, is a microprocessor CPU design philosophy that favors a simpler set of instructions that all take about the same amount of time to execute. ... A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... It has been suggested that some sections of this article be split into a new article entitled instruction set architecture. ... 1985 (MCMLXXXV) was a common year starting on Tuesday of the Gregorian calendar. ... Sun Microsystems, Inc. ...


SPARC is a registered trademark of SPARC International, Inc., an organization established in 1989 to promote the SPARC and to provide conformance testing. SPARC International was intended to open the SPARC architecture to make a larger ecosystem for the design, which has been licensed to several manufacturers, including Texas Instruments, Cypress Semiconductor, and Fujitsu. As a result of SPARC International, the SPARC architecture is fully open and non-proprietary. Incorporation (abbreviated Inc. ... 1989 (MCMLXXXIX) was a common year starting on Sunday of the Gregorian calendar. ... Texas Instruments (NYSE: TXN), better known in the electronics industry (and popularly) as TI, is an American company based in Dallas, Texas, USA, renowned for developing and commercializing semiconductor and computer technology. ... Cypress Semiconductor began operations in 1982 and listed publicly in 1986. ... For the district in Saga, Japan, see Fujitsu, Saga. ...


Implementations of the SPARC architecture were initially designed and used for Sun's Sun-4 workstation and server systems, which superceded the earlier Sun-3 range. Later, SPARC processors were used in SMP servers produced by Sun Microsystems, Solbourne and Fujitsu, among others. SPARC machines have generally used Sun's SunOS or Solaris Operating Systems, but other operating systems such as NEXTSTEP, RTEMS, FreeBSD, OpenBSD, NetBSD, and Linux are also used on SPARC-based systems. Sun-4 was the name given to a series of UNIX computer workstations and servers produced by Sun Microsystems, launched in 1987. ... SGI O2 Workstation A computer workstation, often colloquially referred to as workstation, is a high-end general-purpose microcomputer designed to be used by one person at a time and which offers higher performance than normally found in a personal computer, especially with respect to graphics, processing power and the... This article or section does not cite its references or sources. ... Sun-3 was the name given to a series of UNIX computer workstations and servers produced by Sun Microsystems, launched in 1985. ... Symmetric Multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. ... Sun Microsystems, Inc. ... Solbourne Computer Inc. ... For the district in Saga, Japan, see Fujitsu, Saga. ... SunOS was the version of the UNIX operating system developed by Sun Microsystems for their workstations and server systems until the early 1990s. ... Solaris is a computer operating system developed by Sun Microsystems. ... An operating system (OS) is a set of computer programs that manage the hardware and software resources of a computer. ... NEXTSTEP is the original object-oriented, multitasking operating system that NeXT Computer, Inc. ... RTEMS (Real-Time Executive for Multiprocessor Systems) is a free open source real-time operating system designed for embedded systems. ... FreeBSD is a Unix-like free operating system descended from AT&T UNIX via the Berkeley Software Distribution (BSD) branch through the 386BSD and 4. ... OpenBSD is a freely available Unix-like computer operating system descended from Berkeley Software Distribution (BSD), a Unix derivative developed at the University of California, Berkeley. ... NetBSD is a freely redistributable, open source version of the Unix-like BSD computer operating system. ... Linux (IPA pronunciation: ) is a Unix-like computer operating system family. ...

Contents

Features

The SPARC architecture was heavily influenced by the earlier designs of the RISC I & II from the University of California, Berkeley. These original RISC designs were minimalist, including as few features or op-codes as possible and aiming to execute instructions at a rate of almost one instruction per clock cycle. This made them similar to the MIPS architecture in many ways, including the lack of instructions such as multiply or divide. Another feature of SPARC influenced by this early RISC movement is the branch delay slot. Berkeley RISC was one of two seminal research projects into RISC-based microprocessor design taking place under ARPAs VLSI project. ... Sather tower (the Campanile) looking out over the San Francisco Bay and Mount Tamalpais. ... A MIPS R4400 microprocessor made by Toshiba. ... In computer architecture, a branch delay instruction is an instruction immediately following a conditional branch instruction which is executed whether or not the branch is taken. ...


The SPARC processor usually contains as many as 128 general purpose registers. At any point, only 32 of them are immediately visible to software - 8 are global registers (one of which, g0, is hard-wired to zero, so only 7 of them are usable as registers) and the other 24 are from the stack of registers. These 24 registers form what is called a register window, and at function call/return, this window is moved up and down the register stack. Each window has 8 local registers and shares 8 registers with each of the adjacent windows. The shared registers are used for passing function parameters and returning values, and the local registers are used for retaining local values across function calls. The "Scalable" in SPARC comes from the fact that the SPARC specification allows implementations to scale from embedded processors up through large server processors, all sharing the same core (nonprivileged) instruction set. One of the architectural parameters that can scale is the number of implemented register windows; the specification allows from 3 to 32 windows to be implemented, so the implementation can choose to implement all 32 to provide maximum call stack efficiency, or to implement only 3 to reduce context switching time, or to implement some number between them. Other architectures that include similar register windows include Intel i960, IA-64, and AMD 29000. Simple representation of a stack In computer science, a stack is a temporary abstract data type and data structure based on the principle of Last In First Out (LIFO). ... In computer engineering, the use of register windows is a technique to improve the performance of a particularly common operation, the procedure call. ... Intels i960 (or 80960) was a RISC-based microprocessor design that became popular during the early 1990s as an embedded microcontroller, becoming a best-selling CPU in that field, along with the competing AMD 29000. ... In computing, IA-64 (short for Intel Architecture-64) is a 64-bit processor architecture developed cooperatively by Intel Corporation and Hewlett-Packard (HP), and implemented in the Itanium and Itanium 2 processors. ... AMD 29000 Microprocessor The AMD 29000, often simply 29k, was a popular family of RISC-based 32-bit microprocessors and microcontrollers from Advanced Micro Devices. ...


The architecture has gone through a few revisions. It gained hardware multiply and divide functionality in Version 8. The most substantial upgrade resulted in Version 9, which is a 64-bit (addressing and data) SPARC specification. In computing, a 64-bit component is one in which data are processed or stored in 64-bit units (words). ...


In SPARC Version 8, the floating point register file has 16 double precision registers. Each of them can be used as two single precision registers, providing a total of 32 single precision registers. An odd-even number pair of double precision registers can be used as a quad precision register, thus allowing 8 quad precision registers. SPARC Version 9 added 16 more double precision registers (which can also be accessed as 8 quad precision registers), but these additional registers can not be accessed as single precision registers. A floating-point number is a digital representation for a number in a certain subset of the rational numbers, and is often used to approximate an arbitrary real number on a computer. ... In computing, double precision is a computer numbering format that occupies two storage locations in computer memory at address and address+1. ... In computing, single precision is a computer numbering format that occupies one storage locations in computer memory at address. ... In computing, quad precision is a computer numbering format that occupies four storage locations in computer memory at address, address+1, address+2, and address+3. ...


Tagged add and subtract instructions perform adds and subtracts on values assuming that the bottom two bits do not participate in the computation. This can be useful in the implementation of the run time for ML, Lisp, and similar languages that might use a tagged integer format. ML is a general-purpose functional programming language developed by Robin Milner and others in the late 1970s at the University of Edinburgh, whose syntax is inspired by ISWIM. Historically, ML stands for metalanguage as it was conceived to develop proof tactics in the LCF theorem prover (the language of... Lisp is a family of computer programming languages with a long history and a distinctive fully-parenthesized syntax. ...


The 32-bit SPARC V8 architecture is a purely big-endian architecture. The 64-bit SPARC V9 architecture utilizes big-endian instructions, but can access data in either big-endian or little-endian byte order, chosen either at the application instruction (load/store) level or at the memory page level (via an MMU setting). The latter is often used for accessing data from inherently little-endian devices, such as those on PCI buses. In computing, endianness is the ordering used to represent some kind of data as a sequence of smaller units. ... In computing, endianness is the ordering used to represent some kind of data as a sequence of smaller units. ... In computing, endianness is the ordering used to represent some kind of data as a sequence of smaller units. ... In computing, endianness is the ordering used to represent some kind of data as a sequence of smaller units. ... In computing, endianness is the ordering used to represent some kind of data as a sequence of smaller units. ...


History

There have been three major revisions of the architecture. The first published revision was the 32-bit SPARC Version 7 (V7) in 1986. SPARC Version 8 (V8), an enhanced SPARC architecture definition, was released in 1990. SPARC V8 was standardized as IEEE 1754-1994, an IEEE standard for a 32-bit microprocessor architecture. SPARC Version 9, the 64-bit SPARC architecture, was released by SPARC International in 1993. In early 2006, Sun released an extended architecture specification, UltraSPARC Architecture 2005. UltraSPARC Architecture 2005 includes not only the nonprivileged and most of the privileged portions of SPARC V9, but also all the architectural extensions (such as CMT, hyperprivileged, VIS 1, and VIS 2) present in Sun's UltraSPARC processors starting with the UltraSPARC T1 implementation. UltraSPARC Architecture 2005 includes Sun's standard extensions and remains compliant with the full SPARC V9 Level 1 specification. The architecture has provided continuous application binary compatibility from the first SPARC V7 implementation in 1987 into the Sun UltraSPARC Architecture implementations. The Institute of Electrical and Electronics Engineers or IEEE (pronounced as eye-triple-ee) is an international non-profit, professional organization incorporated in the State of New York, United States. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ...


As of December 2005 Sun announced their UltraSPARC T1 design would be open sourced, and in March 2006 the full source code became available via the OpenSPARC project. OpenSPARC is an open source hardware project started in December 2005. ...


Among various implementations of SPARC, Sun's SuperSPARC and UltraSPARC-I were very popular, and were used as reference systems for SPEC CPU95 and CPU2000 benchmarks. The 296 MHz UltraSPARC-II is the reference system for the SPEC CPU2006 benchmark. The Standard Performance Evaluation Corporation (SPEC) is a non-profit organization that aims to produce fair, impartial and meaningful benchmarks for computers. ...


SPARC microprocessor specifications

Name Model Frequency
[MHz]
Architecture
Version
Year Threads
Per Core × Cores
= Total Threads
Process
[µm]
Transistors
[millions]
Die size
[mm²]
IO Pins Power
[W]
Voltage
[V]
L1 Dcache
[k]
L1 Icache
[k]
L2 Cache
[k]
L3 Cache
[k]
SPARC (various) 14.28–40 V7 1987-1992 1×1=1 0.8–1.3 ~0.1–1.8 -- 160–256 -- -- -- -- none none
microSPARC I (Tsunami) TI TMS390S10 40–50 V8 1992 1×1=1 0.8 0.8 225? 288 2.5 5 2 4 none none
SuperSPARC I (Viking) TI TMX390Z50 / Sun STP1020 33–60 V8 1992 1×1=1 0.8 3.1 -- 293 14.3 5 16 20 0-2048 none
hyperSPARC (Colorado 1) Ross RT620A 40–90 V8 1993 1×1=1 0.5 1.5 -- -- -- 5? 0 8 128-256 none
microSPARC II (Swift) Fujitsu MB86904 / Sun STP1012 60–125 V8 1994 1×1=1 0.5 2.3 233 321 5 3.3 8 16 none none
hyperSPARC (Colorado 2) Ross RT620B 90–125 V8 1994 1×1=1 0.4 1.5 -- -- -- 3.3 0 8 128-256 none
SuperSPARC II (Voyager) Sun STP1021 75–90 V8 1994 1×1=1 0.8 3.1 299 -- 16 -- 16 20 1024-2048 none
hyperSPARC (Colorado 3) Ross RT620C 125–166 V8 1995 1×1=1 0.35 1.5 -- -- -- 3.3 0 8 512-1024 none
TurboSPARC Fujitsu MB86907 160–180 V8 1995 1×1=1 0.35 3.0 132 416 7 3.5 16 16 512 none
UltraSPARC I (Spitfire) Sun STP1030 143–167 V9 1995 1×1=1 0.47 5.2 315 521 30 @167 MHz 3.3 16 16 512-1024 none
UltraSPARC I (Hornet) Sun STP1030 200 V9 1998 1×1=1 0.42 5.2 265 521 -- 3.3 16 16 512-1024 none
hyperSPARC (Colorado 4) Ross RT620D 180–200 V8 1996 1×1=1 0.35 1.7 -- -- -- 3.3 16 16 512 none
UltraSPARC IIs (Blackbird) Sun STP1031 250–400 V9 1997 1×1=1 0.35 5.4 149 521 25 @250 MHz 2.5 16 16 1024 or 4096 none
UltraSPARC IIs (Sapphire-Black) Sun STP1032 / STP1034 360–480 V9 1999 1×1=1 0.25 5.4 126 521 21 @400 MHz 1.9 16 16 1024–8192 none
UltraSPARC IIi (Sabre) Sun SME1040 270–360 V9 1997 1×1=1 0.35 5.4 156 587 21 1.9 16 16 256–2048 none
UltraSPARC IIi (Sapphire-Red) Sun SME1430 333–480 V9 1998 1×1=1 0.25 5.4 -- 587 21 @440 MHz 1.9 16 16 2048 none
UltraSPARC IIe (Hummingbird) Sun SME1701 400–600 V9 2000 1×1=1 0.18 Al -- -- 370 13 max @500 MHz 1.5-1.7 16 16 256 none
UltraSPARC IIi (IIe+) -- 550–650 V9 2002 1×1=1 0.18 Cu -- -- 370 17.6 1.7 16 16 512 none
UltraSPARC III (Cheetah) Sun SME1050 600 V9 2001 1×1=1 0.18 Al 29 330 1368 53 1.6 64 32 8192 none
UltraSPARC III (Cheetah) Sun SME1052 750–900 V9 2001 1×1=1 0.13 Al 29 -- 1368 -- 1.6 64 32 8192 none
UltraSPARC III Cu (Cheetah+) Sun SME1056 1002–1200 V9 2001 1×1=1 0.13 Cu 29 232 1368 80 @900 MHz 1.6 64 32 8192 none
UltraSPARC IIIi (Jalapeno) Sun SME1603 1064–1593 V9 2003 1×1=1 0.13 87.5 206 959 52 1.3 64 32 1024 none
UltraSPARC IV (Jaguar) Sun SME1167 1050–1350 V9 2004 1×2=2 0.13 66 356 1368 108 1.35 64 32 16384 none
UltraSPARC IV+ (Panther) -- 1500–2100 V9 2005 1×2=2 0.09 295 336 1368 90 1.1 64 64 2048 32768
UltraSPARC T1 (Niagara) Sun SME1905 1000–1400 V9 / UA 2005 2005 4×8=32 0.09 300 340 1933 72 1.3 8 16 3072 none
SPARC64-VI -- 2150–2400 V9 2007 2×2=4 0.09 -- -- -- -- -- 128 128 6144 none
UltraSPARC T2 (Niagara II) ? 1400–2000 V9 / UA ???? 2007 8×8=64 0.065 503 342 1831 84 1.1–1.5 ? ? 4096 ?
UltraSPARC RK (Rock) Sun SME1832 ? V9 / UA ???? 2007-8? 2×16=32[1] 0.065 ? ? 2326 ? ? ? ? ? ?
Name Model Frequency
[MHz]
Architecture
Version
Year Threads
Per Core × Cores
= Total Threads
Process
[µm]
Transistors
[millions]
Die size
[mm²]
IO Pins Power
[W]
Voltage
[V]
L1 Dcache
[k]
L1 Icache
[k]
L2 Cache
[k]
L3 Cache
[k]

April 4th, 2007: Customers will now find 1.95GHz and 2.1GHz iterations of the processor available for low-end and midrange machines. Higher-end kit appears available with the 1.95GHz chips only for the moment, excluding the beastly E25K, which is stuck at 1.8GHz. Sun continues to offer older UltraSPARC IV+ chips, running between 1.5GHz and 1.8GHz, across it SunFire line. The UltraSPARC IV+ is a microprocessor manufactured by Sun Microsystems. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ... Sun Microsystems UltraSPARC T2 microprocessor, is a multithreading, multicore CPU. The UltraSPARC T2s predecessor was the UltraSPARC T1. ... Rock is planned multithreading, multicore microprocessor currently in development at Sun Microsystems. ...


Open source implementations

Two fully open source implementations of the SPARC architecture exist. Open source refers to projects that are open to the public and which draw on other projects that are freely available to the general public. ...

  • LEON is a 32-bit, single-thread SPARC Version 8 implementation. Source code is written in VHDL, and licensed under the GPL.
  • OpenSPARC T1 is a 64-bit, 32-thread implementation conforming to the UltraSPARC Architecture 2005 and to SPARC Version 9. Source code is written in Verilog, and licensed under many licenses. Most OpenSPARC T1 source code is licensed under the GPL. Source based on extant open source projects will continue to be licensed under their current licenses. Binary programs are licensed under a binary Software License Agreement.

Leon or Léon or León may refer to: // Léon, Landes, a commune of the Landes département, France Léon (viscounty), Brittany, France Léon (diocese), Brittany, France León, Guanajuato León, Nicaragua León Department Leon, Iloilo León, Spain, city and capital of the... Source code (commonly just source or code) is any series of statements written in some human-readable computer programming language. ... VHDL or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. ... The GNU logo The GNU General Public License (GNU GPL or simply GPL) is a widely-used free software license, originally written by Richard Stallman for the GNU project. ... OpenSPARC is an open source hardware project started in December 2005. ... Verilog is a hardware description language (HDL) used to model electronic systems. ... The GNU logo The GNU General Public License (GNU GPL or simply GPL) is a widely-used free software license, originally written by Richard Stallman for the GNU project. ...

SPARC64 V

SPARC64 V is a 64-bit SPARC V9-compliant processor family developed by Fujitsu and used in their PRIMEPOWER family of servers. For the district in Saga, Japan, see Fujitsu, Saga. ...


Supercomputers

The fastest supercomputers based on SPARC64 processors:

  • National Aerospace Laboratory of Japan. Machine: Fujitsu PRIMEPOWER HPC2500, CPU: 2304 SPARC64 (1.3 GHz). Rmax: 5.406 Teraflops.

References

  1. ^ Sun CEO shows off Rock ahead of Fujitsu launch. The Register (2007-04-10).

Current logo of The Register. ...

See also

  • UltraSPARC T1 – Sun's first multicore and multithread CPU (code-named "Niagara")
  • UltraSPARC T2 – The successor to T1, taped out as of summer 2006
  • OpenSPARC – an open source project based on the UltraSPARC T1 design
  • ERC32 – based on SPARC V7 specification
  • Rock processor – The follow on multi-processor version of T1, expected in 2008
  • Ross Technology, Inc. – SPARC designer/manufacturer of the 1980s and 1990s
  • AardC++ programming tool which uses a spliced-in shared library on SPARCs

Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ... A code name or cryptonym is a word or name used clandestinely to refer to another name or word. ... Sun Microsystems UltraSPARC T2 microprocessor, is a multithreading, multicore CPU. The UltraSPARC T2s predecessor was the UltraSPARC T1. ... In electronics, tape-out is the name of the final stage of the design of an integrated circuit such as a microprocessor, the point at which the description of a circuit is sent for manufacture. ... OpenSPARC is an open source hardware project started in December 2005. ... ERC32 is a 32 bit RISC processor radiation-tolerant developed for space applications. ... Rock is planned multithreading, multicore microprocessor currently in development at Sun Microsystems. ... Ross Technology, Inc. ... Aard (Dutch for Earth) is a programming tool to check memory use for C++ programs. ... C++ (pronounced see plus plus, IPA: ) is a general-purpose, high-level programming language with low-level facilities. ...

External links

BSD operating systems SPARC ports

Linux distributions

v  d  e
RISC
Power Architecture · ARM architecture · DEC Alpha · Atmel AVR · AVR32 ·MIPS architecture · PA-RISC · PIC microcontroller · SPARC · SuperH · i960 · Motorola 88000 ·

  Results from FactBites:
 
SPARC Bylaws (1336 words)
SPARC members are not eligible for positions as media heads, and media heads are not eligible for membership in SPARC.
SPARC is to maintain a policy of fostering both freedom and responsibility among student publications-freedom to pursue and to disseminate information without prior clearance or restraint, and responsibility to do so without engaging in libel, slander, undocumented allegations, attacks on personal integrity, unwarranted invasions of privacy, or techniques of harassment and innuendo.
SPARC, in cooperation with a station adviser and the station staff, is to provide for the monitoring of the station, its personnel, and programming to assure that these are in compliance with all codes and regulations (including licensing of the station and its personnel and all reporting requirements) of the Federal Communications Commission.
SPARC | Scholarly Publishing and Academic Resources Coalition (496 words)
SPARC FAQ for University Administrators and Faculty (May 2, 2006)
More information on SPARC's work for public access is available from the Alliance for Taxpayer Access.
The University of Glasgow, SPARC Europe and LIBER are proud to announce:
  More results at FactBites »

 
 

COMMENTARY     


Share your thoughts, questions and commentary here
Your name
Your comments

Want to know more?
Search encyclopedia, statistics and forums:

 


Press Releases |  Feeds | Contact
The Wikipedia article included on this page is licensed under the GFDL.
Images may be subject to relevant owners' copyright.
All other elements are (c) copyright NationMaster.com 2003-5. All Rights Reserved.
Usage implies agreement with terms, 1022, m