Many electronic systems use internal clocks which are required to be phase-aligned to and/or frequency multiples of some external reference clock. For example, a typical PC CPU of 2004 might have an internal 2.4 GHz core clock which is phase aligned to a bus clock running at 100 MHz. The frequency multiplication is important because multiplying frequencies on chip is much easier than transmitting high frequency clocks on a motherboard. The phase alignment is important so that data can be exchanged reliably between circuits in the high frequency core domain and circuits in the lower frequency bus clock domain.
The circuit which synthesizes the high frequency core clock from and phase aligned to the bus clock is called a phase-locked loop.
A basic PLL consists of a phase detector, a charge pump, a low pass filter, and a voltage-controlled oscillator. The oscillator generates the periodic output signal. If the clock edges from the oscillator (called the feedback edges) fall behind those of the reference, the phase detector causes the charge pump to change the control voltage, so that the oscillator speeds up. Likewise, if the feedback edges creep ahead of those of the reference clock, the phase detector causes the charge pump to change the control voltage to slow down the oscillator. The low-pass filter smooths out the abrupt control inputs from the charge pump, so that the system tends towards a state where the phase detector makes very few corrections.
Most PLLs also include a divider between the VCO and the feedback input to the phase detector. The divider sends through one pulse in N, where N is usually programmable. The effect of the divider is that when the PLL locks, the VCO is going N times faster than the reference clock.
Some PLLs also include a divider between the reference clock and the reference input to the phase detector. If this divider divides by M, it allows the VCO to multiply the reference frequency by N / M. It might seem simpler to just feed the PLL a lower frequency, but in some cases the reference frequency may be constrained by other issues, and then the reference divider is useful.
Clock recovery: Some data streams, especially high-speed serial data streams, are sent without an accompanying clock. The receiver generates a clock from an approximate frequency reference, and then phase-aligns to the transitions in the data stream with a PLL. In order for this scheme to work, the data stream must have a transition frequently enough to correct any drift in the PLL's oscillator. Typically, some sort of redundant encoding is used; 8B10B is very common.
Deskewing: If a clock is sent in parallel with data, that clock can be used to sample the data. Because the clock must be received and amplified before it can drive the flip-flops which sample the data, there will be a finite, and process-, temperature-, and voltage-dependent delay between the detected clock edge and the received data window. This delay limits the frequency at which data can be sent. One way of eliminating this delay is to include a deskew PLL on the receive side, so that the clock at each data flip-flop is phase-matched to the received clock.
Clock generation: Most electronic systems include processors of various sorts that operate at hundreds of megahertz. Typically, the clocks supplied to these processors come from clock generator PLLs, which multiply a lower-frequency reference clock (usually 50 or 100 MHz) up to the operating frequency of the processor. The multiplication factor can be quite large in cases where the operating frequency is multiple gigahertz and the reference crystal is just tens or hundreds of megahertz.
Spread spectrum: All electronic systems emit some unwanted radio frequency energy. Various regulatory agencies (such as the FCC in the United States) put limits on this emitted energy and any interference caused by it. The emitted noise generally appears at sharp spectral peaks (usually at the operating frequency of the device, and a few harmonics). A system designer can use a spread-spectrum PLL to reduce interference with high-Q receivers by spreading the energy over a larger portion of the spectrum. For example, by changing the operating frequency up and down by a small amount (about 1%), a device running at hundreds of megahertz can spread its interference evenly over a few megahertz of spectrum, which drastically reduces the amount of noise seen by FM receivers which have a bandwidth of tens of kilohertz.
Phase detector types
A PLL with a bang-bang charge pump supplies current pulses with fixed total charge, either positive or negative, to the capacitor acting as a low pass filter. A phase detector for a bang-bang charge pump must always have a dead band where the phases of the reference and feedback clocks are close enough that the detector fires either both or neither of the charge pumps, for no total effect. Bang-bang control systems are simple, but are associated with significant minimum peak-to-peak jitter, because once in lock the phase offset hunts between the two extrema values of the dead band.
A proportional phase detector directs the charge pump to supply charge amounts in proportion to the phase error detected. Although some proportional phase detectors have dead bands, some do not. Specifically, some designs arrange to produce both "up" and "down" control pulses when the phase offset is zero. These pulses are small, nominally the same duration, and cause the charge pump to produce equal-charge positive and negative current pulses. A proportional phase detector does not necessarily hunt while in lock, and so PLLs with this kind of control system typically have lower minimum peak-to-peak jitter that is determined by other limiting factors.
Voltage-controlled oscillators (VCOs) are built of a ring of active delay stages. Generally the ring has an odd number of inverting stages, so that there is no single stable state for the internal ring voltages. Instead, a single transition propagates endlessly around the ring. The frequency is controlled by varying either the supply voltage or the capacitive loading on each stage. VCOs generally have the lowest Q of the used oscillators, and so suffer more jitter than the other types. The jitter can be made low enough for many applications (such as driving an ASIC), in which case VCOs enjoy the advantages of having no off-chip components (expensive) or on-chip inductors (low yields on generic CMOS processes). These oscillators also have larger tuning ranges than the other kinds, which improves yield and is sometimes a feature of the end product (for instance, the dot clock on a graphics card which drives a wide range of monitors).
Inductive oscillators (LC oscillators) are built of an LC "tank" circuit, which oscillates by charging and discharging a capacitor through an inductor. These oscillators are typically used when a tunable precision frequency source is necessary, such as with radio transmitters and receivers. On-chip inductors suffer large resistive losses, so that the Q of the resulting tank circuit is generally less than 10. As processes have made larger numbers of metal layers available, on-chip inductors have become more useful. Many LC oscillators use off-chip inductors or bond-wire inductors.
Crystal oscillators are piezoelectric quartz crystals that mechanically vibrate between two slightly different shapes. Crystals have very high Q, and can only be tuned within a very small range of frequencies. Crystal oscillators are typically used as the frequency reference for other PLLs, and can be found in nearly every consumer electronic device. Because the crystal is an off-chip component, it adds some cost and complexity to the system design, but the crystal itself is generally quite inexpensive.
- Surface-accoustic-wave devices (SAWs) are a kind of crystal oscillator, but achieve much higher frequencies by establishing standing waves on the surface of the quartz crystal. These are more expensive than crystal oscillators, and are used in more specialized applications which require a direct and very accurate high frequency reference.
Digitally-controlled oscillators (DCOs) are also commonly used in modern PLLs. These synthesize a digital waveform using a lookup-table driven by a counter that is incremented by an amount determined by the PLL feedback at a (typically crystal-controlled) frequency at least twice that of the frequency to be synthesized. DCOs allow the creation of all-digital PLLs, are are commonly used in modern television and radio demodulators and modems.
Typically, the reference clock enters the chip and drives a phase locked loop (PLL), which then drives the system's clock distribution. The clock distribution is usually balanced so that the clock arrives at every endpoint simultaneously. One of those endpoints is the PLL's feedback input. The function of the PLL is to compare the distributed clock to the incoming reference clock, and vary the phase and frequency of its output until the reference and feedback clocks are phase and frequency matched. From a control theory perspective, the PLL is a special case of the Kalman filter.
PLLs are ubiquitous -- they tune clocks in systems several feet across, as well as clocks in small portions of individual chips. Sometimes the reference clock may not actually be a pure clock at all, but rather a data stream with enough transitions that the PLL is able to recover a regular clock from that stream. Sometimes the reference clock is the same frequency as the clock driven through the clock distribution, other times the distributed clock may be some rational multiple of the reference.
PLLs are generally built of a phase frequency detector, a charge pump, low pass filter, bias generator, voltage-controlled oscillator (VCO), and usually some kind of output converter. There may be a divider in the feedback path or in the reference path, or both, in order to make the PLL's output clock a rational multiple of the reference.
One desirable property of all PLLs is that the reference and feedback clock edges be brought into very close alignment. The average difference in time between the phases of the two signals when the PLL has achieved lock is called the static phase offset. The variance between these phases is called tracking jitter. Ideally, the static phase offset should be zero, and the tracking jitter should be as low as possible.
Another desirable property of all PLLs is that the phase and frequency of the generated clock be unaffected by rapid changes in the voltages of the power and ground supply lines, as well as the voltage of the substrate on which the PLL circuits are fabricated. This is called supply and substrate noise rejection.
Phase-locked loops are widely used for synchronization purposes; in space communications for coherent carrier tracking and threshold extension, bit synchronization, and symbol synchronization.
Phase-locked loops can also be used to demodulate frequency-modulated signals, and to synthesize new frequencies which are a multiple of a reference frequency.
An important part of a phase-locked loop is the phase detector. This compares the phase of the local oscillator to that of the reference signal. In an analog PLL the phase detector is a linear multiplier. This generates a low-frequency signal whose amplitude is related to the phase difference, or phase error, between the oscillator and the reference, and an unwanted high-frequency signal that is filtered out.
There are several types of phase detectors used in digital phase-locked loops. The simplest is an exclusive OR gate, which maintains a 90° phase difference, but cannot lock the signal unless it is already on frequency. A more complicated one uses flip-flops to determine which of the two signals has a zero-crossing earlier or more often. This brings the signal in even when it is off frequency.
Analog phase-locked loop
The equations governing a phase-locked loop are the following:
the input to the PLL is xc(t), the output of the voltage-controlled oscillator (VCO) is xr(t), the output of the phase detector is xm(t). The input to the loop filter is xm(t), the output is y(t). Note that gv is the sensitivity of the VCO and is expressed in Hz/V.
We can deduce how the PLL reacts to a sinusoidal input signal:
The output of the phase detector then is:
This can be rewritten into sum and difference components using trigonometric identities:
Filtering out the sum frequency and leaving the difference frequency, enables us to derive a small-signal model of the phase-locked loop. If we can make , then the can be approximated by its argument resulting in: . The phase-locked loop is said to be locked if this is the case.
Some parts of this article are derived from public domain parts of Federal Standard 1037C in support of MIL-STD-188.