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Encyclopedia > PCI Express
PCI Express

PCI Express logo
Year created: 2004
Created by: Intel

Width: 1 bit
Number of devices: 1 per slot
Capacity 8 GB/s (v1.1, x32)
Style: Serial
Hotplugging? Depends on form factor
External? Depends on form factor
Not to be confused with PCI-X, a different bus architecture.

PCI Express, officially abbreviated as PCI-E or PCIe, is a computer expansion card interface format introduced by Intel in 2004. PCI Express was designed to replace the general-purpose PCI expansion bus, the high-end PCI-X bus and the AGP graphics card interface. Unlike previous PC expansion interfaces, rather than being a bus it is structured around point-to-point serial links called lanes. Image File history File links No higher resolution available. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article is about the unit of information. ... This article is about the unit of measurement. ... In telecommunications and computer science, serial communications is the process of sending data one bit at one time, sequentially, over a communications channel or computer bus. ... For other meanings of PCI, see PCI (disambiguation). ... This article is about the machine. ... An expansion card (also expansion board, adapter card or accessory card) in computing is a printed circuit board that can be inserted into an expansion slot of a computer motherboard to add additional functionality to a computer system. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article is about the computer bus type. ... For other meanings of PCI, see PCI (disambiguation). ... The Accelerated Graphics Port (also called Advanced Graphics Port, often shortened to AGP) is a high-speed point-to-point channel for attaching a graphics card to a computers motherboard, primarily to assist in the acceleration of 3D computer graphics. ... An electrical bus (sometimes spelled buss) is a physical electrical interface where many devices share the same electric connection. ... This article does not cite any references or sources. ...

Contents

Summary

A PCI Express link is built around pairs of serial (1-bit), unidirectional point-to-point connections known as "lanes". This is in sharp contrast to the PCI standard which is a bus-based system in which all the devices share the same bidirectional, 32-bit (or 64-bit), parallel signal path.


In PCIe 1.1 (currently the most common version) each lane sends information at a rate of 250 MB/s (250 million bytes per second) in each direction.
PCIe 2.0 doubles this data rate, introduced in late 2007, PCIe 2.0 is found on newer systems such as those based around the Intel X38 or AMD 780G chipsets.
The latest proposed PCIe 3.0 standard will increase the speed of the links further (tentatively scheduled for release around 2010).[1] This article is about a unit of data. ...


Each PCIe slot carries either one, two, four, eight, sixteen or thirty-two lanes of data between the motherboard and the addin card. Lane counts are written with an "x" prefix e.g. x1 for a single-lane card and x16 for a sixteen-lane card. Thirty-two lanes of 250 MB/s (PCIe 1.1) gives a maximum transfer rate of 8 GB/s (250 MB/s x 32, i.e., 8 billion bytes per second) in each direction. However the largest size in common use for PCIe 1.1 is x16, giving a transfer rate of 4 GB/s (250 MB/s x 16) in each direction. Putting this into perspective, a single lane for PCIe 1.1 has nearly twice the data rate of normal PCI, a four-lane slot has a transfer rate comparable to the fastest version of the old parallel PCI-X 1.0, and an eight-lane slot has a transfer rate comparable to the fastest version of AGP. However the data rates cited must be derated because 8b/10b coding is used in the physical layer. The link transfer speeds cited are to be considered maximum theoretical data rates. In telecommunication, data transfer rate or just transfer rate is the average number of bits, characters, or blocks per unit time passing between corresponding equipment in a data transmission system. ...


PCIe slots come in a variety of physically different sizes referred to by the maximum lane count they support, ie. x1, x2, x4, x8, x16 and x32. A PCIe card will fit into a slot of its size or bigger, but not into a smaller PCIe slot.


The number of lanes actually connected to a slot may also be less than the number supported by the physical slot size. An example is a x8 slot that actually only runs at x1; these slots will allow any x1, x2, x4 or x8 card to be used, though only running at the x1 speed. This type of socket is described as a 'x8 (x1 mode)' slot, meaning it physically accepts up to x8 cards but only runs at x1 speed. The advantage gained is that a larger range of PCIe cards can still be used without requiring the motherboard hardware to support the full transfer rate - in so doing keeping design and implementation costs down.


The number of lanes is "negotiated" during power-up or explicitly during operation. By making the lane count flexible a single standard can provide for the needs of high-bandwidth cards (e.g. graphics cards, 10 Gigabit Ethernet cards and multiport Gigabit Ethernet cards) while also being economical for less demanding cards. This feature allows a x1 card to be inserted into a x4 slot. The system will deprecate the link speed to the x1 card's needs and provide data to the card on 1 lane even though the motherboard is capable of x4 operation on that particular slot. 10 Gigabit Ethernet or 10GbE or 10 GigE is the most recent (as of 2006) and fastest of the Ethernet standards. ... Gigabit Ethernet (GbE or 1 GigE) is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second, as defined by the IEEE 802. ...


As well as the ordinary expansion cards for desktops and servers, the PCIe electrical interface is used in a variety of other form factors including the ExpressCard laptop expansion card interface. PCIe is also often used to connect integrated peripherals on the motherboard. ExpressCard is a hardware standard replacing PC cards (also known as PCMCIA cards), both developed by the Personal Computer Memory Card International Association (PCMCIA). ...


Specifications of the format are being maintained and developed by a group of more than 900 industry-leading companies called the PCI Special Interest Group (PCI-SIG).


Overview

A PCI Express x16 slot
A PCI Express x16 slot
A PCI Express x1 slot
A PCI Express x1 slot

The PCIe physical layer consists of a network of serial interconnects. A hub on the mainboard acts as a crossbar switch allowing point-to-point device interconnections to be rerouted on the fly. This dynamic point-to-point connection behavior leads to parallelism since more than one pair of devices may communicate with each other at the same time. (In contrast, older PC interfaces had all devices permanently wired to the same bus; therefore, only one device could talk at a time.) This is similar to the difference between conversing over a telephone where you can only call one person at a time, and conversing in a meeting, where you can talk to a person beside you directly. The format also allows channel grouping, where multiple lanes are bonded to a single device pair in order to provide higher bandwidth. Image File history File links Size of this preview: 800 × 131 pixelsFull resolution (2144 × 351 pixels, file size: 247 KB, MIME type: image/jpeg) The PCI-Express Bus on a Gigabyte-brand Mainboard picture taken on Nov, 10 2005 by Clemens PFEIFFER Bildrechte frei bei Quellenangebe Clemens PFEIFFER, Wien. Belegexemplar... Image File history File links Size of this preview: 800 × 131 pixelsFull resolution (2144 × 351 pixels, file size: 247 KB, MIME type: image/jpeg) The PCI-Express Bus on a Gigabyte-brand Mainboard picture taken on Nov, 10 2005 by Clemens PFEIFFER Bildrechte frei bei Quellenangebe Clemens PFEIFFER, Wien. Belegexemplar... Image File history File links No higher resolution available. ... Image File history File links No higher resolution available. ... A crossbar switch is one of the principal architectures used to construct switches of many types. ...


The bonded serial format was chosen over a traditional parallel format due to the phenomenon of timing skew. Timing skew is a direct result of the limitations imposed by the speed of an electrical signal traveling down a wire, which it does at a finite speed. Because different traces in an interface have different lengths, parallel signals transmitted simultaneously from a source arrive at their destinations at different times. When the interconnection clock rate rises to the point where the wavelength of a single bit is less than this difference in path length, the bits of a single word do not arrive at their destination simultaneously, making parallel recovery of the word difficult. Thus, the speed of the electrical signal, combined with the difference in length between the longest and shortest trace in a parallel interconnect, leads to a naturally imposed maximum bandwidth. Serial channel bonding avoids this issue by not requiring the bits to arrive simultaneously. PCIe is just one example of a general trend away from parallel buses to serial interconnects. For other examples, see HyperTransport, Serial ATA, USB, SAS, FireWire or RapidIO. The multichannel serial design also increases flexibility by allowing slow devices to be allocated fewer lanes than fast devices. Timing skew is a problem that can occur on many kinds of computer buses. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... For other uses of SATA or Sata, see SATA (disambiguation). ... USB redirects here. ... 2. ... The 6-pin and 4-pin FireWire 400 Connectors The alternative ethernet-style cabling used by 1394c FireWire is Apple Inc. ... The RapidIOâ„¢ architecture is a high-performance, packet-switched, interconnect technology for interconnecting chips on a circuit board and circuit boards using a backplane. ...


PCIe is supported primarily by Intel, which started working on the standard as the Arapahoe project after pulling out of the InfiniBand system. PCIe is intended to be used as a local interconnect only. It was designed to be software compatible with the preexisting PCI standard, making the conversion of PCI cards and systems to PCI Express as simple as replacing the physical layer without requiring a change to the supporting software. The increased bandwidth on PCI Express has led to unification, as it is fast enough to replace almost all existing internal buses, including AGP and PCI. Intel envisions a single PCI Express controller talking to all external devices in the future, as opposed to the northbridge/southbridge solution used in current machines. Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The panel of an InfiniBand switch InfiniBand is a switched fabric communications link primarily used in high-performance computing. ... In computer science, a local bus is a computer bus that connects directly, or almost directly, from the CPU to one or more slots on the expansion bus. ... The Accelerated Graphics Port (also called Advanced Graphics Port, often shortened to AGP) is a high-speed point-to-point channel for attaching a graphics card to a computers motherboard, primarily to assist in the acceleration of 3D computer graphics. ... This article or section does not cite any references or sources. ... This article does not cite any references or sources. ...


Unlike preceding PC expansion interface standards, PCIe is a point-to-point "bus". This type of connection removes the need for "arbitrating" the bus or waiting for the bus to free. This means that while standard PCI-X (133 MHz 64 bit) and PCIe x4 have roughly the same data transfer rate, PCIe x4 will give better performance if multiple device pairs are communicating simultaneously or if communication within a single device pair is bidirectional. Two-way communication is a form of transmission in which both parties involved transmit information. ...


History

While in development, PCI Express (PCIe) was referred to internally at Intel as Arapahoe or 3GIO for 3rd Generation I/O.


PCIe is a technology under constant development and improvement. The current standard version in general use at time of writing is PCIe 1.1; however, the PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007. PCIe 2.0 doubles the data rate of each lane from 2.5 GT/s to 5 GT/s. PCIe 2.0 is backward compatible with PCIe 1.1 as a physical interface slot and from within software, so older cards will still be able to work in machines fitted with this new version. Further information on PCIe 2.0 is detailed below. The PCI-SIG or Peripheral Component Interconnect Special Interest Group is an electronics industry consortium responsible for specifying the Peripheral Component Interconnect (PCI), PCI-X, and PCI Express (PCIe) computer busses. ... is the 15th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... Gigatransfer (GT) and Megatransfer (MT) are terms used in computer technology, referring to a number of data transfers (or operations). ...


Hardware protocol summary

The PCIe link is built around dedicated unidirectional couples of serial (1-bit), point-to-point connections known as "lanes". This is in sharp contrast to the PCI connection, which is a bus-based system where all the devices share the same bidirectional, 32-bit (or 64-bit), parallel bus.


PCI Express is a layered protocol, consisting of a Transaction Layer, a Data Link Layer, and a Physical Layer. The Data Link Layer is further divided to include a Media Access Control sublayer. The Physical Layer is further divided into a logical sublayer and an electrical sublayer. The PHY logical sublayer contains a Physical Coding Sublayer (PCS). (Terms borrowed from the IEEE 802 model of networking protocol.) In computer science a layered protocol is a system where one or more programs act as interfaces between two end systems. ... IEEE 802 refers to a family of IEEE standards about local area networks and metropolitan area networks. ...


Physical Layer

The PCIe Physical Layer (PHY) (PCIEPHY , PCI Express PHY or PCIe PHY) specification is divided into two sublayers, corresponding to electrical and logical specifications. The logical sublayer is sometimes further divided into a MAC (Media Access Control) sublayer and a PCS (Physical Coding Sublayer), although this division is not formally part of the PCIe specification. A specification published by Intel, the PHY Interface for PCI Express (PIPE)[2] , defines the MAC/PCS functional partitioning and the interface between these two sublayers. The PIPE specification also identifies the PMA (Physical Media Attachment) layer, which includes the Serializer/Deserializer and other analog circuitry; however, since SerDes implementations vary greatly among ASIC vendors, PIPE does not specify an interface between the PCS and PMA. A SERializer/DESerializer (SERDES) is a device used in high speed communications. ...


At the electrical level, each lane consists of two unidirectional LVDS or PCML pairs at 2.52½ Gbit/s. Transmit and receive are separate differential pairs, for a total of 4 data wires per lane. Low voltage differential signaling, or LVDS, is an electrical signalling system that can run at very high speeds over cheap, twisted-pair copper cables. ... Current mode logic (CML) is one logic class of the CMOS family. ... A gigabit is a unit of information or computer storage, abbreviated Gbit or sometimes Gb. ... Differential pair is a pair of conductors with special characteristics, used for differential signaling. ...

PCI Express slots (from top to bottom: x4, x16, x1, and x16), compared to a traditional 32-bit PCI slot (bottom), as seen on DFI's LanParty nF4 Ultra-D
PCI Express slots (from top to bottom: x4, x16, x1, and x16), compared to a traditional 32-bit PCI slot (bottom), as seen on DFI's LanParty nF4 Ultra-D
An XFX brand NVIDIA GeForce 6600GT PCI Express x16 video adapter card

A connection between any two PCIe devices is known as a "link", and is built up from a collection of 1 or more lanes. All devices must minimally support single-lane (x1) link. Devices may optionally support wider links composed of 2, 4, 8, 12, 16, or 32 lanes. This allows for very good compatibility in two ways: ImageMetadata File history File links Download high resolution version (927x629, 449 KB) PCI Express x4, x16 and x1 slots, as well as a standard 32-bit PCI slot. ... ImageMetadata File history File links Download high resolution version (927x629, 449 KB) PCI Express x4, x16 and x1 slots, as well as a standard 32-bit PCI slot. ... For other uses of DFI, see DFI (disambiguation). ... Image File history File linksMetadata Download high resolution version (1948x1273, 1644 KB) Summary PCI Express video adapter card Licensing I, the creator of this work, hereby grant the permission to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1. ... Image File history File linksMetadata Download high resolution version (1948x1273, 1644 KB) Summary PCI Express video adapter card Licensing I, the creator of this work, hereby grant the permission to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1. ... The XFX logo & slogan XFX is a subsidiary of the Hong Kong-headquartered Pine Technology Holdings Limited Group that specializes in the manufacture of graphics cards based on designs by chipset manufacturer NVIDIA. Like BFG and eVGA, XFX sell cards which come overclocked to speeds higher than the standard cards... The American multinational Nvidia Corporation (NASDAQ: NVDA) (pronounced ) specializes in the manufacture of graphics-processor technologies for workstations, desktop computers, and handheld devices. ... The GeForce 6 Series is nVidias newest series of graphics processors. ...

  • a PCIe card will physically fit (and work correctly) in any slot that is at least as large as it is (e.g. an x1 sized card will work in any sized slot);
  • a slot of a large physical size (e.g. x16) can be wired electrically with fewer lanes (e.g. x1, x4, or x8) as long as it provides the power and ground connections required by the larger physical slot size.

In both cases, PCIe will negotiate the highest mutually supported number of lanes.


It is often not possible to place a physically larger PCIe card (e.g. a 16x sized card) into a smaller slot, even though the two would be signal-compatible if it were possible. Some motherboards have open-ended PCIe slots which allow for a physically larger card to be inserted in a smaller PCIe slot.


The width of a PCIe connector is 8.8 mm, while the height is 11.25 mm, and the length is variable. The 'minor' half of the connector is 11.65 mm in length and contains 22 pins, while the length of the 'major' half is variable. The thickness of the card going into the connector is 1.8mm.[3][4]

Lanes Pins Total Pins in 'major' half Total Length Length of 'major' half
x1 36 14 25 mm 7.65 mm
x4 64 42 39 mm 21.65 mm
x8 98 76 56 mm 38.65 mm
x16 164 142 89 mm 71.65 mm

Data transmission

PCIe sends all control messages, including interrupts, over the same links used for data. The serial protocol can never be blocked, so latency is still comparable to PCI, which has dedicated interrupt lines.


Data transmitted on multiple-lane links is interleaved, meaning that each successive byte is sent down successive lanes. The PCIe specification refers to this interleaving as "data striping." While requiring significant hardware complexity to synchronize (or deskew) the incoming striped data, striping can significantly increase the throughput of the link. Due to padding requirements, striping may not necessarily reduce the latency of small data packets on a link. In telecommunication, the term skew has the following meanings: 1. ...


As with all high data rate serial transmission protocols, clocking information must be embedded in the signal. At the physical level, PCI Express utilizes the very common 8b/10b encoding scheme to ensure that strings of consecutive ones or consecutive zeros are limited in length. This is necessary to prevent the receiver from losing track of where the bit edges are. In this coding scheme every 8 (uncoded) payload bits of data are replaced with 10 (encoded) bits of transmit data, consuming an extra 25% of the overall electrical bandwidth. In telecommunications, 8b/10b is a line code that maps 8-bit symbols to 10-bit symbols to achieve DC-balance (see DC coefficient) and bounded disparity, and yet provide enough state changes to allow reasonable clock recovery. ...


Many other protocols (such as SONET) use a different form of encoding known as "scrambling" to embed clock information into data streams. The PCI Express specification also defines a scrambling algorithm, but it is used to reduce EMI (Electromagnetic interference) by preventing repeating data patterns in the transmitted data stream. Synchronous Optical Networking, commonly known as SONET, is a standard for communicating digital information over optical fiber. ... In telecommunications, a scrambler (often referred to as a randomizer) is a device that randomizes a data stream before transmitting. ... Radio Frequency Interference (RFI) is electromagnetic radiation which is emitted by electrical circuits carrying rapidly changing signals, as a by-product of their normal operation, and which causes unwanted signals (interference or noise) to be induced in other circuits. ...


Signaling rate

The first-generation PCIe transfers data at a 2.5 GT/s (gigatransfer per second) signaling rate per lane. PCIe version 2.0 provides an increase in the signaling rate to 5 GT/s per lane. A third-generation PCIe specification is in development with the goal of further increasing the rate. Gigatransfer (GT) and Megatransfer (MT) are terms used in computer technology, referring to a number of data transfers (or operations). ...


Data Link Layer

The Data Link Layer implements the sequencing of the Transaction Layer Packets (TLPs) that are generated by the Transaction Layer, data protection via a 32-bit cyclic redundancy check code (CRC, known in this context as LCRC) and an acknowledgment protocol (ACK and NAK signaling). TLPs that pass an LCRC check and a sequence number check result in an acknowledgment, or ACK, while those that fail these checks result in a negative acknowledgment, or NAK. TLPs that result in a NAK, or timeouts that occur while waiting for an ACK, result in the TLPs being replayed from a special buffer in the transmit data path of the Data Link Layer. This guarantees delivery of TLPs in spite of electrical noise, barring any malfunction of the device or transmission medium. A cyclic redundancy check (CRC) is a type of function that takes an input of data stream of any length and produces as output a value of a certain fixed size. ... Acknowledge character (ACK): A transmission control character transmitted by the receiving station as an affirmative response to the sending station. ... In telecommunications, a negative-acknowledge character (NAK) is a transmission control character sent by a station as a negative response to the station with which the connection has been set up. ...


ACK and NAK signals are communicated via a low-level packet known as a data link layer packet, or DLLP. DLLPs are also used to communicate flow control information between the transaction layers of two connected devices, as well as some power management functions.


Transaction Layer

PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response.


PCI Express utilizes credit-based flow control. In this scheme, a device advertises an initial amount of credit for each of the receive buffers in its Transaction Layer. The device at the opposite end of the link, when sending transactions to this device, will count the number of credits consumed by each TLP from its account. The sending device may only transmit a TLP when doing so does not result in its consumed credit count exceeding its credit limit. When the receiving device finishes processing the TLP from its buffer, it signals a return of credits to the sending device, which then increases the credit limit by the restored amount. The credit counters are modular counters, and the comparison of consumed credits to credit limit requires modular arithmetic. The advantage of this scheme (compared to other methods such as wait states or handshake-based transfer protocols) is that the latency of credit return does not affect performance, provided that the credit limit is not encountered. This assumption is generally met if each device is designed with adequate buffer sizes. Modular arithmetic (sometimes called modulo arithmetic, or clock arithmetic because of its use in the 24-hour clock system) is a system of arithmetic for integers, where numbers wrap around after they reach a certain value — the modulus. ...


First-generation PCIe is often quoted to support a data rate of 250 MB/s in each direction, per (x1) lane. This figure is a calculation from the physical signaling rate (2.5 Gbaud) divided by the encoding overhead (10 bits per byte.) This means a sixteen lane (x16) PCIe card would then be theoretically capable of 250 MB/s * 16 = 4 GB/s in each direction. While this is correct in terms of data bytes, more meaningful calculations will be based on the usable data payload rate, which depends on the profile of the traffic, which is a function of the high-level (software) application and intermediate protocol levels. Like other high data rate serial interconnect systems, PCIe has a protocol and processing overhead due to the additional transfer robustness (CRC and Acknowledgments). Long continuous unidirectional transfers (such as those typical in high-performance storage controllers) can approach >95% of PCIe's raw (lane) data rate. These transfers also benefit the most from increased number of lanes (x2, x4, etc.) But in more typical applications (such as a USB or Ethernet controller), the traffic profile is characterized as short data packets with frequent enforced acknowledgments.[citation needed] This type of traffic reduces the efficiency of the link, due to overhead from packet parsing and forced interrupts (either in the device's host interface or the PC's CPU.) This loss of efficiency is not particular to PCIe. For the town in France, see Baud, Morbihan. ... USB redirects here. ... Ethernet is a large, diverse family of frame-based computer networking technologies that operate at many speeds for local area networks (LANs). ...


Form factors

A PCI-E x1 card with an RS-232 port
A PCI-E x1 card with an RS-232 port
  • Low height card
  • Mini Card: a replacement for the Mini PCI form factor (with x1 PCIe, USB 2.0 and SMBus buses on the connector)
  • ExpressCard: successor to the PC card form factor (with x1 PCIe and USB 2.0; hot-pluggable)
  • PCI Express ExpressModule: a hot-pluggable modular form factor defined for servers and workstations
  • XMC: similar to the CMC/PMC form factor (with x4 PCIe or Serial RapidI/O)
  • AdvancedTCA: a complement to CompactPCI for larger applications; supports serial based backplane topologies
  • AMC: a complement to the AdvancedTCA specification; supports processor and I/O modules on ATCA boards (x1,x2,x4 or x8 PCIe).
  • PCI Express External Cabling[5]
  • Mobile PCI Express Module (MXM) A laptop graphics module specification created by NVIDIA.
  • Advanced eXpress I/O Module (AXIOM) graphics module design endorsed by ATI Technologies (ATI was purchased by AMD in 2006).

Image File history File links Size of this preview: 621 × 600 pixelsFull resolution‎ (1,143 × 1,104 pixels, file size: 236 KB, MIME type: image/jpeg) RS232 to PCI Express card I, the copyright holder of this work, hereby release it into the public domain. ... Image File history File links Size of this preview: 621 × 600 pixelsFull resolution‎ (1,143 × 1,104 pixels, file size: 236 KB, MIME type: image/jpeg) RS232 to PCI Express card I, the copyright holder of this work, hereby release it into the public domain. ... RS-232 (also referred to as EIA RS-232C or V.24) is a standard for serial binary data interchange between a DTE (Data terminal equipment) and a DCE (Data communication equipment). ... A wlan PCI Express Mini Card and its connector. ... Mini PCI Wi-Fi card Type IIIB Mini PCI is a standard for a computer bus for attaching peripheral devices to a computer motherboard and is an adaptation of the Peripheral Component Interconnect (PCI) bus. ... The System Management Bus (abbreviated to SMBus or SMB) is a simple two-wire bus used for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptops rechargeable battery subsystem (see Smart Battery Data). ... ExpressCard is a hardware standard replacing PC cards (also known as PCMCIA cards), both developed by the Personal Computer Memory Card International Association (PCMCIA). ... The PCMCIA is the Personal Computer Memory Card International Association, an industry trade association that creates standards for notebook computer peripheral devices. ... A PCI mezzanine card or PMC is a printed circuit board manufactured to the IEEE P1386. ... Advanced Telecommunications Computing Architecture is the largest specification effort in the history of the PCI Industrial Computer Manufacturers Group (PICMG), with more than 100 companies participating. ... This article or section does not cite its references or sources. ... Advanced Mezzanine Cards are printed circuit boards (PCBs) that follow a specification of the PCI Industrial Computers Manufacturers Group (PICMG), with more than 100 companies participating. ... Advanced Telecommunications Computing Architecture is the largest specification effort in the history of the PCI Industrial Computer Manufacturers Group (PICMG), with more than 100 companies participating. ... A Mobile PCI Express Module (MXM) is an interconnect standard for GPUs in laptops using PCI Express. ... The American multinational Nvidia Corporation (NASDAQ: NVDA) (pronounced ) specializes in the manufacture of graphics-processor technologies for workstations, desktop computers, and handheld devices. ... ATI Technologies Inc. ... Advanced Micro Devices, Inc. ...

Competing protocols

Several communications standards have emerged based on high bandwidth serial architectures. These include but are not limited to HyperTransport, InfiniBand, RapidIO, and StarFabric. HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The panel of an InfiniBand switch InfiniBand is a switched fabric communications link primarily used in high-performance computing. ... The RapidIOâ„¢ architecture is a high-performance, packet-switched, interconnect technology for interconnecting chips on a circuit board and circuit boards using a backplane. ...


Essentially the differences are based on the tradeoffs between flexibility and extensibility vs. latency and overhead. An example of such a tradeoff is adding complex header information to a transmitted packet to allow for complex routing (PCI Express is not capable of this). This additional overhead reduces the effective bandwidth of the interface and complicates bus discovery and initialization software. Also making the system hot-pluggable requires that software track network topology changes. Examples of buses suited for this purpose are InfiniBand and StarFabric.


Another example is making the packets shorter to decrease latency (as is required if a bus is to be operated as a memory interface). Smaller packets mean that the packet headers consume a higher percentage of the packet, thus decreasing the effective bandwidth. Examples of bus protocols designed for this purpose are RapidIO and HyperTransport.


PCI Express falls somewhere in the middle, targeted by design as a system interconnect (local bus) rather than a device interconnect or routed network protocol. Additionally, its design goal of software transparency constrains the protocol and raises its latency somewhat. In computer science, a local bus is a computer bus that connects directly, or almost directly, from the CPU to one or more slots on the expansion bus. ...


Status

As of 2007, PCI Express has replaced AGP as the most common interface for graphics cards on new systems. With a few exceptions, all graphics cards being released today (2008) from ATI and NVIDIA use PCI Express. NVIDIA uses the high bandwidth data transfer of PCIe for its newly developed Scalable Link Interface (SLI) technology, which allows multiple graphics cards of the same chipset and model number to be run in tandem, allowing increased performance. ATI also has developed a multi-GPU system based on PCIe called CrossFire. Towards the end of 2007, AMD released a motherboard chipset, the AMD 790FX, which supports up to four PCIe x16 slots, allowing tri-GPU and quad-GPU configurations for ATI cards. Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... The Accelerated Graphics Port (also called Advanced Graphics Port, often shortened to AGP) is a high-speed point-to-point channel for attaching a graphics card to a computers motherboard, primarily to assist in the acceleration of 3D computer graphics. ... A graphics/video/display card/board/adapter is a computer component designed to convert the logical representation of visual information into a signal that can be used as input for a display medium. ... ATI Technologies Inc. ... The American multinational Nvidia Corporation (NASDAQ: NVDA) (pronounced ) specializes in the manufacture of graphics-processor technologies for workstations, desktop computers, and handheld devices. ... For other uses, see SLI. NVIDIA SLI Logo Scalable Link Interface (SLI) is a brand name for a multi-GPU solution developed by NVIDIA for linking two (or more) video cards together to produce a single output. ... CrossFire (also CrossFire X after release of the Spider desktop platform on November 19, 2007) is a brand name for ATI Technologies multi-GPU solution, which competes with its rival nVidias Scalable Link Interface (SLI). ...


Uptake for other forms of PC expansion has been much slower and PCI remains dominant. PCI Express is commonly used for onboard gigabit ethernet and wi-fi but add-in cards are still generally PCI, particularly at the lower end of the market. Sound cards, modems, serial port cards and other cards with low-speed interfaces are still nearly all PCI. For this reason most motherboards supporting PCI Express offer legacy PCI slots as well. Gigabit Ethernet (GbE or 1 GigE) is a term describing various technologies for transmitting Ethernet frames at a rate of a gigabit per second, as defined by the IEEE 802. ... Wi-Fi (IPA: ) is the common name for a popular wireless technology used in home networks, mobile phones, video games and more. ...


ExpressCard has been introduced on several mid- to high-range laptops such as Apple's MacBook Pro line. Unlike desktops, however, laptops frequently only have one expansion slot. Replacing the PC card slot with ExpressCard slot means a loss in compatibility with PC-card devices. ExpressCard is a hardware standard replacing PC cards (also known as PCMCIA cards), both developed by the Personal Computer Memory Card International Association (PCMCIA). ... Apple Computer, Inc. ... The MacBook Pro is a line of Macintosh portable computers by Apple Inc. ... The PCMCIA is the Personal Computer Memory Card International Association, an industry trade association that creates standards for notebook computer peripheral devices. ...


External PCI Express

Main article: Cabled PCI Express

The name used by PCI-SIG (PCI Special Interest Group) is PCI Express External Cabling. The most commonly used name is External PCI Express (28400 Google-hits, 2008-03) or shortened External PCIe. Another name used is Cabled PCI Express (2400 Google-hits, 2008-03) or shortened Cabled PCIe. The PCI-SIG or Peripheral Component Interconnect Special Interest Group is an electronics industry consortium responsible for specifying the Peripheral Component Interconnect (PCI), PCI-X, and PCI Express (PCIe) computer busses. ...


Specifications

2007-02 The first PCI Express External Cabling specifications was released by PCI-SIG February 2007. "This specification helps the industry create new products that will take PCIe technology out of the box – enabling PCIe solutions for IO expansion drawers, external graphics processors, tethered mobile docking, communications equipment and embedded applications".


Standard cables and connectors have been defined for x1, x4, x8, and x16 link widths, with a transfer rate of 250 MB/s per lane. The PCI-SIG also expects the norm will evolve to reach the 500 MB/s as found in PCI Express 2.0. The maximal length of cabling isn't known yet.


External PCIe Video Cards

Potentially External PCIe could give a notebook the graphic power of a desktop, by connecting a notebook with any PCIe desktop video card (enclosed in its own external housing), however, only one finalized product and two concept products exist. All three deliver the power of the video card to external displays only, and all connect to a notebook through an ExpressCard interface which limits the bandwidth from an inserted x16 video card (4 GB/s in each direction), to just x1 (250 MB/s in each direction): Magma ExpressBox Magma. Luxium by MSI TheInquirer, CustomPcMag. XG Station by Asus Asus, VR-Zone ExpressCard is a hardware standard replacing PC cards (also known as PCMCIA cards), both developed by the Personal Computer Memory Card International Association (PCMCIA). ...


Additionally, Nvidia has developed Quadro Plex, external PCIe Video Cards that can be used for advanced graphic applications. These video cards require a PCI Express x8 or x16 slot, for the interconnection cable.[6] The American multinational Nvidia Corporation (NASDAQ: NVDA) (pronounced ) specializes in the manufacture of graphics-processor technologies for workstations, desktop computers, and handheld devices. ... For a definition of the word quadro, see the Wiktionary entry quadro. ...


AMD has recently announced the ATI XGP technology, see http://ati.amd.com/technology/xgp/index.html


PCI Express 2.0

PCI-SIG announced the availability of the PCI Express Base 2.0 specification on 15 January 2007.[7] PCIe 2.0 doubles the bus standard's bandwidth from 0.25 Gbyte/s to 0.5 Gbyte/s, meaning a x32 connector can transfer data at up to 16 Gbyte/s in each direction. The PCI-SIG or Peripheral Component Interconnect Special Interest Group is an electronics industry consortium responsible for specifying the Peripheral Component Interconnect (PCI), PCI-X, and PCI Express (PCIe) computer busses. ... is the 15th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ...


PCIe 2.0 is backward and forward compatible with PCIe v1.x. Graphic cards and motherboards designed for v2.0 will be able to work with v1.1 and v1.0, and vice versa. In some rare cases it is possible that a PCI-E 2.0 card will not work correctly on a PCI-E 1.0a slot. This is only limited to certain video cards.


The PCI-SIG also said PCIe 2.0 also features improvements to the point-to-point data transfer protocol and its software architecture.[8]


In June 2007 Intel released the specification of the P35 chipset which does not support PCIe 2.0 only PCIe 1.1.[9] Some people may be confused by the P35 block diagram[10] which states the Intel P35 has a PCIe x16 graphics link (8 GB/s) and 6 PCIe x1 links (500 MB/s each), for simple verification one can view the P965 block diagram which shows the same number of lanes and bandwidth but was released before PCIe 2.0 was finalized. Intel's first PCIe 2.0 capable chipset is the X38 and boards are already shipping from various vendors (Abit, Asus, Gigabyte) as of October 21, 2007.[11] AMD started supporting PCIe 2.0 with its RD700 chipset series. NVIDIA has revealed that the MCP72 will be their first PCIe 2.0 equipped chipset.[12] Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article does not cite any references or sources. ... This is a list of computer motherboard chipsets made by Intel. ... ABIT is a Taiwanese computer components manufacturer, active since the late 1980s. ... ASUSTeK Computer Incorporated (Asus) (TSE: 2357) (traditional Chinese: ) is a Taiwan-based company that produces motherboards, graphics cards, optical drives, PDAs, notebook computers, servers, networking products, mobile phones, computer cases, computer components and computer cooling systems. ... Gigabyte (or Giga-byte) Technology is a Taiwan-based manufacturer of computer hardware products best known for its motherboards. ... RD700 series is a chipset series made by ATI and is targeted to launch between the end of 2007 to the first half of 2008. ... The nForce 700 is a chipset series designed by NVIDIA, to be released before the end of 2007, shortly after the launch of GeForce 8800 GT (codenamed G92) video card. ...


PCI Express 3.0

In August 2007 PCI-SIG announced that PCI Express 3.0 will carry a bit rate of 8 gigatransfers per second. The spec will be backwards-compatible with existing PCIe implementations and a final spec is due in 2009. New features for PCIe 3.0 specification include a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery, and channel enhancements for currently supported topologies.[1] Gigatransfer (GT) and Megatransfer (MT) are terms used in computer technology, referring to a number of data transfers (or operations). ...


Following a six-month technical analysis of the feasibility of scaling the PCIe interconnect bandwidth, PCI-SIG's analysis found out that 8 gigatransfers per second can be manufactured in mainstream silicon process technology, and can be deployed with existing low-cost materials and infrastructure, while maintaining full compatibility (with negligible impact) to the PCIe protocol stack.


PCIe 2.0 delivers 5 GT/s but employed an 8b/10b encoding scheme which took 20 percent overhead on the overall raw bit rate. By removing the requirement for the 8b/10b encoding scheme (relying solely on the still-used scrambler), PCIe 3.0's 8 GT/s bit rate effectively delivers double PCIe 2.0 bandwidth. According an official press release by PCI-SIG on August 8, 2007:

"The final PCIe 3.0 specifications, including form factor specification updates, may be available by late 2009, and could be seen in products starting in 2010 and beyond."[13]

PCI-SIG expects the PCIe 3.0 specifications to undergo rigorous technical vetting and validation before being released to the industry. This process, which was followed in the development of prior generations of the PCIe Base and various form factor specifications, includes the corroboration of the final electrical parameters with data derived from test silicon and other simulations conducted by multiple members of the PCI-SIG.


See also

This article does not cite any references or sources. ... This article does not cite any references or sources. ... This article or section does not adequately cite its references or sources. ... NuBus is a 32-bit parallel computer bus, originally developed at MIT as a part of the NuMachine workstation project, and eventually used by Apple Computer and NeXT Computer. ... This article or section does not cite any references or sources. ... This article is about the computer bus type. ... The Accelerated Graphics Port (also called Advanced Graphics Port, often shortened to AGP) is a high-speed point-to-point channel for attaching a graphics card to a computers motherboard, primarily to assist in the acceleration of 3D computer graphics. ... This is a list of device bandwidths: the channel capacity (or, more informally, bandwidth) of some computer devices employing methods of data transport is quantified in units of kilobits per second (kbit/s), megabits per second (Mbit/s), or gigabits per second (Gbit/s) as appropriate. ... This article or section does not cite its references or sources. ... Advanced Telecommunications Computing Architecture is the largest specification effort in PICMGs history, with more than 100 companies participating. ... For other meanings of PCI, see PCI (disambiguation). ...

References

  1. ^ a b "PCI Express 3.0 Bandwidth: 8.0 Gigatransfers/s", ExtremeTech, 2007-08-09. Retrieved on 2007-09-05. 
  2. ^ PHY Interface for the PCI Express Architecture, version 2.00. Retrieved on 2008-05-21.
  3. ^ Mechanical Drawing for PCI Express Connector. Retrieved on 2007-12-07.
  4. ^ FCi schematic for PCIe connectors. Retrieved on 2007-12-07.
  5. ^ PCI Express External Cabling 1.0 Specification. Retrieved on 2007-02-09.
  6. ^ Quadro Plex website.
  7. ^ PCI-SIG (2007-01-15). "PCI Express Base 2.0 specification announced" (PDF). Press release. Retrieved on 2007-02-09. — note that in this press release the term "aggregate bandwidth" refers to the sum of incoming and outgoing bandwidth; using this terminology the aggregate bandwidth of full duplex 100BASE-TX is 200 Mbit/s
  8. ^ Tony Smith. "PCI Express 2.0 final draft spec published", The Register, 2006-10-11. Retrieved on 2007-02-09. 
  9. ^ Intel® P35 Express Chipset Product Brief (PDF). Intel. Retrieved on 2007-09-05.
  10. ^ Richard Swinburne. "First look - Intel P35 chipset", bit-tech.net, 2007-05-21. Retrieved on 2007-06-19. 
  11. ^ Gary Key & Wesley Fink. "Intel P35: Intel's Mainstream Chipset Grows Up", AnandTech, 2007-05-21. Retrieved on 2007-05-21. 
  12. ^ Anh Huynh. "NVIDIA "MCP72" Details Unveiled", AnandTech, 2007-02-08. Retrieved on 2007-02-09. 
  13. ^ "PCI-SIG Announces PCI Express 3.0 Bit Rate For Products In 2010 And Beyond", 2007-08-08. Retrieved on 2008-03-24. 

Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 221st day of the year (222nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 248th day of the year (249th in leap years) in the Gregorian calendar. ... 2008 (MMVIII) is the current year, a leap year that started on Tuesday of the Anno Domini (or common era), in accordance with the Gregorian calendar. ... is the 141st day of the year (142nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 341st day of the year (342nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 341st day of the year (342nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 40th day of the year in the Gregorian calendar. ... The PCI-SIG or Peripheral Component Interconnect Special Interest Group is an electronics industry consortium responsible for specifying the Peripheral Component Interconnect (PCI), PCI-X, and PCI Express (PCIe) computer busses. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 15th day of the year in the Gregorian calendar. ... PDF is an abbreviation with several meanings: Portable Document Format Post-doctoral fellowship Probability density function There also is an electronic design automation company named PDF Solutions. ... For information on Wikipedia press releases, see Wikipedia:Press releases. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 40th day of the year in the Gregorian calendar. ... Current logo of The Register. ... Year 2006 (MMVI) was a common year starting on Sunday of the Gregorian calendar. ... is the 284th day of the year (285th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 40th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 248th day of the year (249th in leap years) in the Gregorian calendar. ... This article is being considered for deletion in accordance with Wikipedias deletion policy. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 141st day of the year (142nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 170th day of the year (171st in leap years) in the Gregorian calendar. ... AnandTech. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 141st day of the year (142nd in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 141st day of the year (142nd in leap years) in the Gregorian calendar. ... AnandTech. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 39th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 40th day of the year in the Gregorian calendar. ... Year 2007 (MMVII) was a common year starting on Monday of the Gregorian calendar in the 21st century. ... is the 220th day of the year (221st in leap years) in the Gregorian calendar. ... 2008 (MMVIII) is the current year, a leap year that started on Tuesday of the Anno Domini (or common era), in accordance with the Gregorian calendar. ... is the 83rd day of the year (84th in leap years) in the Gregorian calendar. ...

External links


  Results from FactBites:
 
PCI Express - Free net encyclopedia (1995 words)
PCI Express, or PCIe, (formerly known as 3GIO for 3rd Generation I/O, not to be mistaken for PCI-X or PXI) is an implementation of the PCI computer bus that uses existing PCI programming concepts, but bases it on a completely different and much faster serial physical-layer communications protocol.
At the physical level, PCI Express utilizes the very common 8B/10B encoding scheme to ensure that strings of consecutive ones or consecutive zeros are limited in length, so that the receiver does not lose track of where the bit edges are.
PCI Express implements split transactions (transactions with request and response separated by time), allowing the link to carry other traffic while the target device gathers data for the response.
  More results at FactBites »

 
 

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