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Encyclopedia > Opteron

The Opteron is AMD's x86 server processor line, and was the first processor to implement the AMD64 instruction set architecture (known generically as x86-64). It was released on April 22, 2003 with the SledgeHammer core (K8) and was intended to compete in the server market, particularly in the same segment as the Intel Xeon processor. Processors based on the K10 microarchitecture were announced on September 10, 2007 featuring a new quad-core configuration. “AMD” redirects here. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... CPU redirects here. ... AMD64 Logo AMD64 (also x86-64 or x64) is a 64-bit microprocessor architecture and corresponding instruction set designed by Advanced Micro Devices. ... An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... is the 112th day of the year (113th in leap years) in the Gregorian calendar. ... Year 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ... In information technology, a server is an application or device that performs services for connected clients as part of a client-server architecture. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article is about the Intel microprocessor. ... The AMD K10 is AMDs next generation of processors. ... is the 253rd day of the year (254th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era in the 21st century. ... Diagram of an Intel Core 2 dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache. ...

Contents

Technical description

The two key capabilities

Opteron combines two important capabilities in a single processor die:

  1. native execution of legacy x86 32-bit applications without speed penalties
  2. native execution of x86-64 64-bit applications (linear-addressing beyond 4 GiB RAM)

The first capability is notable because at the time of Opteron's introduction, the only other 64-bit processor architecture marketed with 32-bit x86 compatibility (Intel's Itanium) ran x86 legacy-applications only with significant speed degradation. The second capability, by itself, is less noteworthy, as all major RISC players (Sun SPARC, DEC Alpha, HP PA-RISC, IBM POWER, SGI MIPS, etc.) have had 64-bit implementations for many years. In combining these two capabilities, however, the Opteron has earned recognition for its ability to run the vast installed base of x86 applications economically, while simultaneously offering an upgrade-path to 64-bit computing. 32-bit is a term applied to processors, and computer architectures which manipulate the address and data in 32-bit chunks. ... In computing, a 64-bit component is one in which data are processed or stored in 64-bit units (words). ... The term gib may refer to: a castrated male cat or ferret an abbreviation for gibibyte (GiB) or gibibit (Gib) an abbreviation for Gibraltar an abbreviation for Gib Board, itself an abbreviation of Gibraltar Board, all Winston Wallboards[1] tradenames for drywall (plasterboard). ... RAM redirects here. ... In computing, a 64-bit component is one in which data are processed or stored in 64-bit units (words). ... 32-bit is a term applied to processors, and computer architectures which manipulate the address and data in 32-bit chunks. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... Sun UltraSPARC II Microprocessor SPARC (Scalable Processor ARChitecture) is a pure big-endian RISC microprocessor architecture originally designed in 1985 by Sun Microsystems. ... DEC Alpha AXP 21064 Microprocessor die photo Package for DEC Alpha AXP 21064 Microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp... PA-RISC is a microprocessor architecture developed by Hewlett-Packards Systems & VLSI Technology Operation. ... POWER is a RISC instruction set architecture designed by IBM. The name is a acronym for Performance Optimization With Enhanced RISC. POWER is also the name of a series of microprocessors that implements the instruction set architecture. ... A MIPS R4400 microprocessor made by Toshiba. ...


The Opteron processor possesses an integrated DDR SDRAM / DDR2 SDRAM (Socket AM2/F) memory controller. This both reduces the latency penalty for accessing the main RAM and eliminates the need for a separate northbridge chip. DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. ... “DDR2” redirects here. ... The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... This article or section does not cite any references or sources. ... This article or section does not adequately cite its references or sources. ... RAM Latency is the amount of wait time that a computer experiences when trying to access data in its RAM. RAM latency is measured in front side bus clock cycles. ... Look up RAM, Ram, ram in Wiktionary, the free dictionary. ... This article or section does not cite any references or sources. ...


Multi-processor features

In multi-processor systems (more than one Opteron on a single motherboard), the CPUs communicate using the Direct Connect Architecture over high-speed HyperTransport links. Each CPU can access the main memory of another processor, transparent to the programmer. The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing as instead of having one bank of memory for all CPUs, each CPU has its own memory. The Opteron CPU directly supports up to an 8-way configuration, which can be found in mid-level servers. Enterprise-level servers use additional (and expensive) routing chips to support more than 8 CPUs per box. A motherboard is the central or primary circuit board making up a complex electronic system, such as a modern computer. ... CPU redirects here. ... The Direct Connect Architecture is the I/O architecture of the Athlon64 and Opteron microprocessors from AMD. It consists of the combination of three elements: The microprocessor is directly connected to DRAM memory through an integrated memory controller. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... Symmetric multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. ...


In a variety of computing benchmarks, the Opteron architecture has demonstrated better multi-processor scaling than the Intel Xeon[citation needed]. This is primarily because adding an additional Opteron processor increases bandwidth, while that is not always the case for Xeon systems, and the fact that the Opterons use a switched fabric, rather than a shared bus. In particular, the Opteron's integrated memory controller, when using Non-Uniform Memory Access (NUMA), allows the CPU to access local RAM quickly. In contrast, multiprocessor Xeon system CPUs share only two common buses for both processor-processor and processor-memory communication. As the number of CPUs increases in a Xeon system, contention for the shared bus causes computing efficiency to drop. This article is about the Intel microprocessor. ... Switched Fabric is a Fibre Channel topology where many devices connect with each other via Fibre Channel switches. ... PCI Express bus card slots (from top to bottom: x4, x16, x1 and x16), compared to a traditional 32-bit PCI bus card slot (bottom) In computer architecture, a bus is a subsystem that transfers data or power between computer components inside a computer or between computers, and a bus... Non-Uniform Memory Access or Non-Uniform Memory Architecture (NUMA) is a computer memory design used in multiprocessors, where the memory access time depends on the memory location relative to a processor. ... Look up RAM, Ram, ram in Wiktionary, the free dictionary. ... Bus contention is an undesirable state of the bus of a computer, in which more than one memory mapped device or the CPU is attempting to place output values onto the bus at once. ...


Multi-core Opterons

In May of 2005, AMD introduced its first "Multi-Core" Opteron CPUs. At the present time, the term "Multi-Core" at AMD in practice means "dual-core"; each physical Opteron chip actually contains two separate processor cores. This effectively doubles the computing-power available to each motherboard processor socket. One socket can now deliver the performance of two processors, two sockets can deliver the performance of four processors, and so on. Since motherboard costs go up dramatically as the number of CPU sockets increases, multicore CPUs now allow much higher performing systems to be built with more affordable motherboards. A Dual-core CPU combines two independent processors and their respective caches and cache controllers onto a single silicon die, or integrated circuit. ...


AMD's model number scheme has changed somewhat in light of its new multicore lineup. At the time of its introduction, AMD's fastest multicore Opteron was the model 875, with two cores running at 2.2 GHz each. AMD's fastest single-core Opteron at this time was the model 252, with one core running at 2.6 GHz. For multithreaded applications, the model 875 would be much faster than the model 252, but for single threaded applications the model 252 would perform faster. A gigahertz is a billion hertz or a thousand megahertz, a measure of frequency. ... Many programming languages, operating systems, and other software development environments support what are called threads of execution. ...


Next-Generation AMD Opteron processors are offered in three series: the 1200 Series (up to 1P/2-core), the 2200 Series (up to 2P/4-core), and the 8200 Series (4P/8-core to 8P/16-core). The 1200 Series is built on AMD's new Socket AM2. The 2200 Series and 8200 Series are built on AMD's new Socket F (1207). The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... This article or section does not cite any references or sources. ...


AMD is expected to launch quad core[1] Opteron chips in August 2007 [2] with hardware vendors to follow suit with servers in the following month. Based on a core design codenamed Barcelona, new power and thermal management techniques are planned for the chips. Existing dual core DDR2 based platforms will be upgradeable to quad core chips[3]. It has been suggested that this article or section be merged into Multi-core. ...


Socket 939

AMD has also released Socket 939 Opterons, reducing the cost of motherboards for low-end servers and workstations. Except for the fact they have 1MiB L2 Cache (versus 512KiB for the Athlon64) the Socket 939 Opterons are identical to the San Diego and Toledo core Athlon 64s, but are run at lower clockspeeds than the cores are capable of, making them more stable. Since this means that they overclock very well, they were popular and in great demand.[citation needed] They are also the only dual core Socket 939 processors still easily available now that the Athlon 64 X2s for that platform have been discontinued. [1] Socket 939 was introduced by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... AMD Athlon XP Overclocking BIOS Setup on ABIT NF7-S. FSB frequency (External clock) has increased from 133 MHz to 148 MHz, and clock multiplier factor has changed from 13. ...


Socket AM2

Socket AM2 Opterons are available for servers that will only have a single-chip setup. These chips may prove to be as successful as the previous generation socket 939 Opterons due to the Opteron's overclockability. Codenamed Santa Ana, dual core AM2 Opterons feature 2×1 MiB L2 cache, unlike the majority of their Athlon 64 X2 cousins which feature 2x512 KiB L2 cache. Image File history File links Gnome_globe_current_event. ... Image File history File links This is a lossless scalable vector image. ... formula here</math></math></math></math></math>The three-letter acronym MIB may refer to any of several concepts: Management Information Base, a computing information repository used (for example) by Simple Network Management Protocol An abbreviation for mebibyte (MiB) or mebibit (Mib) Men in Black, a group of mysterious agents... Athlon 64 X2 Logo Athlon 64 X2 E6 3800+ The Athlon 64 X2 is the first dual-core desktop CPU manufactured by AMD. It is essentially a processor consisting of two Athlon 64 cores joined together on one die with additional control logic. ... According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ...


Socket F (1207)

Socket F (1207) is AMD’s second generation of Opteron processors (codename Santa Rosa, Barcelona and Shanghai) the “Lidded Land Grid Array” socket adds support for DDR2 SDRAM, quad core processors,(see ‘Multi-core Opterons’ above) improved HyperTransport connectivity and Virtualization (AMD-V™) Physically the socket and processor package are nearly identical, although not generally compatible with socket 1207 FX This article or section does not cite any references or sources. ... The land grid array (LGA) is a physical interface for microprocessors of the Intel Pentium 4 family. ... “DDR2” redirects here. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... In computing, virtualization is a broad term that refers to the abstraction of computer resources. ... This article does not cite any references or sources. ...


Micro-architecture update

The Opteron line is saw a update with the implementation of the AMD K10 microarchitecture. New processors, launched in the third quarter of 2007, incorporate a variety of improvements, particularly in memory prefetching, speculative loads, SIMD execution and branch prediction, yielding an appreciable performance improvement over K8-based Opterons, within the same power envelope.[4] The AMD K10 is AMDs next generation of processors. ... -1...


In the meantime, AMD has also utilized a new scheme to characterize the power consumption of new processors under "average" daily usage, named Average CPU Power (ACP). The Average CPU Power (abbreviated ACP), is a scheme to characterize power consumption of new processors under average daily usage (especially server processors), the rating scheme is defined by AMD for use in its line of processors based on the K10 microarchitecture (Opteron 8300 and 2300 series processors). ...


Models

First generation single-core Opterons follow the three-digit "Opteron xyy" model numbers and the newer generations (all dual cores) are four-digit in the form "Opteron xnyy".[5]


The first digit (the x) specifies the maximum number of CPUs on the target machine:

The n digit is the release number (omitted in first release). The major differences between release one and release two include different socket type (socket 940 vs. socket F), single-core vs. dual core, quad-core upgradeability, support for DDR1 vs. DDR2 memory and for AMD Virtualization. x86 virtualization is the method by which x86-based guest operating systems are run under another host x86 OS, with little or no modification of the guest OS. The x86 processor architecture did not originally meet the Popek and Goldberg virtualization requirements. ...


The last two digits in the model number (the yy) give an indication of the relative performance comparison among models of the processors.


Models with a HE label refers to a low-power deviative with lower TDP value, while products with an SE label refers to a high performance processor with higher TDP values. The Thermal Design Power (TDP) represents the maximum amount of power the thermal solution in a computer system is required to dissipate. ...


Opteron (130 nm SOI)

Single-core — SledgeHammer (1yy, 2yy, 8yy)

MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... The first 3DNow! CPU 3DNow! is the name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. ... In information theory and coding, an error-correcting code or ECC is a code in which each data signal conforms to specific rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected. ...

Opteron (90 nm SOI, DDR)

Single-core — Venus (1yy), Troy (2yy), Athens (8yy)
Dual-core — Denmark (1yy), Italy (2yy), Egypt (8yy)

MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... The first 3DNow! CPU 3DNow! is the name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. ... SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... Socket 939 was introduced by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. ... Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. ... In information theory and coding, an error-correcting code or ECC is a code in which each data signal conforms to specific rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code) or for storage of data, a feature normally only found in Harvard architecture processors. ... Socket 939 was introduced by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. ... Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code) or for storage of data, a feature normally only found in Harvard architecture processors. ...

Opteron (90 nm SOI, DDR2)

Dual-core — Santa Ana (12yy), Santa Rosa (22yy, 82yy)

MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... The first 3DNow! CPU 3DNow! is the name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. ... SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... This article or section does not cite any references or sources. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (or code) or for storage of data, a feature normally only found in Harvard architecture processors. ...

Opteron (65 nm SOI)

Quad-core — Budapest (13yy) [6], Barcelona (23yy, 83yy)
  • CPU-Steppings: BA
  • L1-Cache: 64 + 64 KiB (Data + Instructions) per core
  • L2-Cache: 512 KiB, fullspeed per core
  • L3-Cache: 2048 KiB, shared
  • MMX, Extended 3DNow!, SSE, SSE2, SSE3, AMD64, SSE4a
  • Socket F, ? GHz HyperTransport 3.0
  • Registered DDR2 SDRAM required, ECC possible
  • Split power plane dynamic power management
  • VCore: 1.2 V
  • First Release: September 10, 2007
  • Clockrate: 1700 - 2000 MHz

MMX is a SIMD instruction set designed by Intel, introduced in 1997 in their Pentium MMX microprocessors. ... The first 3DNow! CPU 3DNow! is the name of a multimedia extension created by AMD for its processors, starting with the K6-2 in 1998. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE2, Streaming SIMD Extensions 2, is one of the IA-32 SIMD (Single Instruction, Multiple Data) instruction sets. ... SSE3, also known by its Intel code name Prescott New Instructions (PNI), is the third iteration of the SSE instruction set for the IA-32 architecture. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... The AMD K10 is AMDs next generation of processors. ... This article or section does not cite any references or sources. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... “DDR2” redirects here. ... In information theory and coding, an error-correcting code or ECC is a code in which each data signal conforms to specific rules of construction so that departures from this construction in the received signal can generally be automatically detected and corrected. ... Josephson junction array chip developed by NIST as a standard volt. ... This article is about the SI unit of frequency. ...

Supercomputers

On the November 2007 TOP500 list, 15.8% of the world's 500 fastest known supercomputer installations were AMD64 Opteron-based systems (down from 22.6% on 11/06), while 64.4% were Intel EM64T/Intel 64 Xeon-based. The TOP500 project ranks and details the 500 most powerful publicly-known computer systems in the world. ... For other uses, see Supercomputer (disambiguation). ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... This article is about the Intel microprocessor. ...


Supercomputers based on Opteron mentioned in the top 10 fastest supercomputers in the world:

  • #6: Sandia National Laboratories, USA. Red Storm - Sandia/ Cray Red Storm, AMD x86_64 Opteron Dual Core 2400 MHz. Cray Inc. 26,569 total cores. Rpeak: 127.531 TeraFlops.
  • #7: Oak Ridge National Laboratory, USA. Jaguar - Cray XT4/XT3. AMD x86_64 Opteron Dual Core 2600 MHz (5.2 GFlops/unit). Cray Inc. 23,016 total cores. Rpeak: 119,350 TFlop.
  • #9: NERSC/LBNL, USA. Franklin - Cray XT4. AMD x86_64 Opteron Dual Core 2600 MHz. Cray Inc. 19,320 total cores. Rpeak: 100,464 TFlop.

It has been suggested that Sandia Base be merged into this article or section. ... For other uses, see Flop. ... A combination of federal, state and private funds is providing $300 million for the construction of 13 facilities on ORNLs new main campus. ... A row of Seaborg computers at NERSC. The National Energy Research Scientific Computing Center, or NERSC for short, is a designated user facility operated by Lawrence Berkeley National Laboratory and the Department of Energy. ... The Berkeley Lab is perched on a hill overlooking the Berkeley central campus and San Francisco Bay. ...

Opteron without Optimized Power Management

AMD has released some Opteron processors without Optimized Power Management(OPM) support, which use DDR1 memory.The following table describes those processors lacking OPM.

Max P-State
Frequency
Min P-State
Frequency
Model Package-Socket Core # Manufacturing
Process
Part Number(OPN)
1400 MHz N/A 140 Socket 940 1 130 nm OSA140CEP5AT
1400 MHz N/A 240 Socket 940 1 130 nm OSA240CEP5AU
1400 MHz N/A 840 Socket 940 1 130 nm OSA840CEP5AV
1600 MHz N/A 142 Socket 940 1 130 nm OSA142CEP5AT
1600 MHz N/A 242 Socket 940 1 130 nm OSA242CEP5AU
1600 MHz N/A 842 Socket 940 1 130 nm OSA842CEP5AV
1600 MHz N/A 242 Socket 940 1 90 nm OSA242FAA5BL
1600 MHz N/A 842 Socket 940 1 90 nm OSA842FAA5BM
1600 MHz N/A 260 Socket 940 2 90 nm OSK260FAA6CB
1600 MHz N/A 860 Socket 940 2 90 nm OSK860FAA6CC

Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... The 130 nanometer (130 nm or 0. ... Since 2002 and up to 2004, the 90 nanometer (90 nm) process has been a buzzword in the electronic, the LSI and semiconductor manufacturing, and fabrication industries. ...

Opteron recall

AMD has recalled some E4 stepping-revision single-core Opteron processors, including x52 (2.6 GHz) and x54 (2.8 GHz) models which use DDR1 memory. The following table describes affected processors, as they are listed in AMD Opteron x52 and x54 Production Notice.[7]

Max P-State
Frequency
Uni-Processor Dual Processor Multi-Processor Package-Socket
2600 MHz 152 252 852 Socket 940
2800 MHz N/A 254 854 Socket 940
2600 MHz 152 N/A N/A Socket 939
2800 MHz 154 N/A N/A Socket 939

The affected processors may produce inconsistent results in the presence of three specific conditions occurring simultaneously: Socket 940 is a 940-pin socket for 64-bit AMD server processors. ... Socket 939 was introduced by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. ...

  • The execution of floating point-intensive code sequences
  • Elevated processor temperatures
  • Elevated ambient temperatures

A software verification tool for identifying the AMD Opteron processors listed in the above table that may be affected under these specific conditions is available only to AMD OEM partners.[citation needed] AMD will replace those processors at no charge.[citation needed] Original equipment manufacturer, or OEM, is a term that refers to containment-based re-branding, namely where one company uses a component of another company within its product, or sells the product of another company under its own brand. ...


Future

Future Opteron processors, will see an implementation of the Montreal core based on a 45 nm fabrication node, manufactured using the MCM technique. Further, the server line of processors will incorporate the newly announced Bulldozer core with native 4 cores or more configurations, each supporting SSE5 aimed at better HPC and cryptographic computations. Image File history File links Gnome_globe_current_event. ... POWER5 MCM with four processors and four 36 MB external L3 cache modules on a ceramic substrate. ... Bulldozer is the codename AMD has given to one of the next-generation CPU cores after K10 microarchitecture for the companys M-SPACE design methodology, with the core specifically aimed at 10 Watts to 100 Watts TDP computing products. ... The SSE5 (short for Streaming SIMD Extensions 5), announced on August 30, 2007, is a new 128-bit extension to the AMD64 instruction set (itself a 64-bit extension to the 32-bit Intel x86 instruction set) for the AMD Bulldozer processor, due to begin production in 2009. ... The field of high performance computing (HPC) comprises computing applications on (parallel) supercomputers and computer clusters. ...


See also

Opteron is the name of a family of CPUs within the AMD64 line, designed by AMD for the server market. ...

References

  1. ^ AMD Details Native Quad-core Design Features for Breakthrough Performance and Advanced Power Efficiencies. Retrieved on 2007-03-06.
  2. ^ http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543~118193,00.html AMD to Ship Industry’s First Native x86 Quad-Core Processors In August, AMD
  3. ^ Quad-Core Upgradeability. Retrieved on 2007-03-06.
  4. ^ Merritt, Rick. "AMD tips quad-core performance", EETimes.com. Retrieved on 2007-03-16. 
  5. ^ AMD Opteron™ Processor FAQs. AMD. Retrieved on 16 March 2007.
  6. ^ Compiled roadmap of Server processors
  7. ^ Advanced Micro Devices (2006-04). AMD Opteron Processor Models x52 and x54 Production Notice. Press release. Retrieved on 2006-11-30.

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  Results from FactBites:
 
Sun and x64 Technology - Overview (255 words)
Powered by the AMD Opteron or Intel Xeon platforms, these systems give you top performance, scalability, power efficiency, manageability, and longevity benefits.
Plus, they let you meet your high performance computing, server consolidation, and web infrastructure goals, whether you run Solaris, Linux, or Windows.
AMD Opteron single- and dual-core processing for Sun x64 systems
Opteron - Wikipedia, the free encyclopedia (1191 words)
The AMD Opteron is the first eighth-generation x86 processor (K8 core), and the first of AMD's AMD64 (x86-64) processors, released April 22, 2003.
The Opteron approach to multi-processing is not the same as standard symmetric multiprocessing as instead of having one bank of memory for all CPUs, each CPU has its own memory.
Socket F is the new socket for the higher-end server-grade Opterons.
  More results at FactBites »

 
 

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