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Encyclopedia > Nios II

Nios II is the second-generation soft-core embedded processor after Nios from Altera. Nios is a soft configurable 16-bit processor designed to target FPGAs from Altera. ... Altera headquarters in San Jose A Flex EPF10K20 FPGA (an Altera product) Altera Corporation (NASDAQ: ALTR) is a leading manufacturer of programmable logic devices. ...

Contents

Nios II CPU Family

Nios II processors implement a 32-bit instruction set based on a RISC architecture. Because it is a soft-core processor, FPGA developers can choose from a myriad of system configurations, picking the best-fit CPU core as well as selecting processor peripherals. There are three Nios II CPU cores: Nios II/f (fast), Nios II/e (economy) and Nios II/s (standard). Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A field-programmable gate array or FPGA is a gate array that can be reprogrammed after it is manufactured, rather than having its programming fixed during the manufacturing — a programmable logic device. ...


The Nios II/f core is designed for maximum performance at the expense of core size.


Features of Nios II/f include:

  • Separate instruction and data caches (512 bytes to 64 Kbytes)
  • Access to up to 2 Gbytes of external address space
  • Optional tightly coupled memory for instructions and data
  • Six-stage pipeline to achieve maximum DMIPS/MHz
  • Single-cycle hardware multiply and barrel shifter
  • Optional hardware divide option
  • Dynamic branch prediction
  • Up to 256 custom instructions and unlimited hardware accelerators
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace


The Nios II/e core is designed for smallest possible logic utilization of FPGAs. This is especially efficient for low-cost Cyclone II FPGA applications. JTAG, an acronym for Joint Test Action Group, is the usual name used for the IEEE 1149. ...


Features of Nios II/e include:

  • Up to 2 Gbytes of external address space
  • JTAG debug module
  • Complete systems in fewer than 700 LEs
  • Optional debug enhancements
  • Up to 256 custom instructions

Nios II/s core is designed to maintain a balance between performance and cost. JTAG, an acronym for Joint Test Action Group, is the usual name used for the IEEE 1149. ...


Features of Nios II/s include:

  • Instruction cache
  • Up to 2 Gbytes of external address space
  • Optional tightly coupled memory for instructions
  • 5-stage pipeline
  • Static branch prediction
  • Hardware multiply, divide, and shift options
  • Up to 256 custom instructions
  • JTAG debug module
  • Optional JTAG debug module enhancements, including hardware breakpoints, data triggers, and real-time trace

JTAG, an acronym for Joint Test Action Group, is the usual name used for the IEEE 1149. ...

Key Features of Nios II:

  • Custom Instructions

The soft-core nature of the Nios II processor lets designers integrate custom logic into the arithmetic logic unit (ALU). Similar to native Nios II instructions, custom instructions accept values from up to two 32-bit source registers and optionally write back a result to a 32-bit destination register. By using custom instructions, The system designers can fine-tune the system hardware to meet performance goals and also the designer can easily handle the instruction as a macro in C/C++.

  • Custom Peripherals

System designers also can create their own custom peripherals that can be integrated with Nios II processor systems. For performance-critical systems that spend most CPU cycles executing a specific section of code, it is a common technique to create a custom peripheral that implements the same function in hardware. Using this approach, performance is doubled: the hardware implementation is faster than software; and the processor is free to perform other functions in parallel while the custom peripheral operates on data.


Avalon Switch Fabric Interface

Nios II uses the Avalon switch fabric as the interface to its embedded peripherals. Compared to a traditional bus in a processor-based system, which lets only one bus master access the bus at a time, the Avalon switch fabric, using a slave-side arbitration scheme, lets multiple masters operate simultaneously.


Development Processes

The development tools for Nios II embedded system involves two processes: (1) Hardware Generation, and (2) Software Creation.


Hardware Generation Process. Nios II hardware designers use the SOPC (System-on-Programmable-Chips) Builder development tool to specify, configure, and generate the embedded system using a graphical user interface (GUI).


Software Creation Process. Nios II software development tasks can be accomplished within an Eclipse-based Nios II integrated development environment (IDE).


Open Source Support

The development environment for Nios II is based om the Eclipse IDE and the GNU toolchain, and ╬╝CLinux has been ported to the processor. The vast majority of pre-existing Open Source programs for Linux will compile and run on Nios II without modifying the source code. Eclipse is a free software / open source platform-independent software framework for delivering what the project calls rich-client applications, as opposed to thin client browser-based applications. ... The GNU toolchain is a blanket term given to the programming tools produced by the GNU project. ... µClinux (which stands for MicroControllerLinux and is pronounced as you-see-Linux) is a Linux distro operating system for microcontrollers (µCs, embedded systems) without a memory management unit (MMU). ... Open source refers to projects that are open to the public and which draw on other projects that are freely available to the general public. ... Linux (also known as GNU/Linux) is a Unix-like computer operating system. ...


See also

Nios is a soft configurable 16-bit processor designed to target FPGAs from Altera. ...

External links

  • Altera's site about Nios II
  • Nios users' community forum
  • RTEMS real-time operating system

  Results from FactBites:
 
Packing Processing Power - Altera Introduces Nios II (1057 words)
Nios II comes in three basic sizes (compared with two flavors of the original Nios): “Fast” with the highest processing performance, “Standard” with a balance between price and performance, and “Economy” with the lowest logic utilization (and therefore lowest effective cost).
Architecturally, the Nios II is a 32-bit pipelined RISC machine with full 32-bit datapath, 32 general purpose registers, 3 instruction formats, and “on chip” hardware multiply, shift, and rotate.
Nios II also has separate instruction and data caches that are configurable for performance/area tradeoffs.
  More results at FactBites »

 
 

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