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Encyclopedia > Microarchitecture

In computer engineering, microarchitecture (sometime abbreviated to µarch or uarch) is a description of the electrical circuitry of a computer, central processing unit, or digital signal processor that is sufficient for completely describing the operation of the hardware. Computer engineering (also called electronic and computer engineering) is a discipline that combines elements of both electrical engineering and computer science. ... An electrical network or electrical circuit is an interconnection of analog electrical elements such as resistors, inductors, capacitors, diodes, switches and transistors. ... This article is about the machine. ... “CPU” redirects here. ... A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real-time. ...


In academic circles, the term computer organization is used, while in the computer industry, the term microarchitecture is more often used. Microarchitecture and instruction set architecture (ISA) together constitute the field of computer architecture. An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ... A typical vision of a computer architecture as a series of abstraction layers: hardware, firmware, assembler, kernel, operating system and applications (see also Tanenbaum 79). ...

Contents

History of the term

Many computers of the 1950s to 1970s used microprogramming to implement their control logic which decoded the program instructions and executed them. The bits within the microprogram words were the electrical signals which controlled the units that actually did the computations. The term microarchitecture was used to describe the units that were controlled by the microprogram words. the first thing that was invented was the automatic DILDO. Education grew explosively because of a very strong demand for high school and college education. ... The 1970s decade refers to the years from 1970 to 1979, also called The Seventies. ... A microprogram is a program consisting of microcode that controls the different parts of a computers central processing unit (CPU). ... Control logic or Business logic is the part of a software architecture that controls what the program will do. ...


Relation to instruction set architecture

Microarchitecture is distinct from a computer's instruction set architecture. The instruction set architecture is the abstract image of a computing system that is seen by a machine language (or assembly language) programmer, including the instruction set, memory address modes, processor registers, and address and data formats. The computer organization is a lower level, more concrete, description of the system than the ISA. The computer organization shows the constituent parts of the system and how they are interconnected and how they interoperate in order to implement the architectural specification. [1][2] [3] An instruction set is (a list of) all instructions, and all their variations, that a processor can execute. ... A system of codes directly understandable by a computers CPU is termed this CPUs native or machine language. ... See the terminology section, below, regarding inconsistent use of the terms assembly and assembler. ... An instruction set is (a list of) all instructions, and all their variations, that a processor can execute. ... In computer architecture, a processor register is a small amount of very fast computer memory used to speed the execution of computer programs by providing quick access to frequently used values—typically, these values are involved in multiple expression evaluations occurring within a small region on the program. ...


Different machines may have the same instruction set architecture, and thus be capable of executing the same programs, yet have different microarchitectures. These different microarchitectures (along with advances in semiconductor manufacturing technology) are what allows newer generations of processors to achieve higher performance levels as compared to previous generations. In theory, a single microarchitecture (especially if it includes microcode) could be used to implement 2 different instruction sets, by programming 2 different control stores. A microprogram is a program consisting of microcode that controls the different parts of a computers central processing unit (CPU). ... A control store is the part of a CPUs control unit that stores the CPUs microprogram. ...


The microarchitecture of a machine is usually represented as a block diagram that describes the interconnections of the registers, buses, and functional blocks of the machine. This description includes the number of execution units, the type of execution units (such as floating point, integer, branch prediction, single instruction multiple data (SIMD), the nature of the pipeline (which might include such stages as instruction fetch, decode, assign, execution, completion in a very simple pipeline), the cache memory design (level 1, level 2 interfaces), and the peripheral support. In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the program. ... A floating-point number is a digital representation for a number in a certain subset of the rational numbers, and is often used to approximate an arbitrary real number on a computer. ... The integers are commonly denoted by the above symbol. ... In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ... -1... This article is about the computer term. ...


The actual physical circuit layout, hardware construction, packaging, and other physical details is called the implementation of that microarchitecture. Two machines may have the same microarchitecture, and hence the same block diagram, but different hardware implementations.[4]


Aspects of microarchitecture

The pipelined datapath is the most commonly used datapath design in microarchitecture today. This technique is used in most modern microprocessors, microcontrollers, and DSPs. The pipelined architecture allows multiple instructions to overlap in execution, much like an assembly line. The pipeline includes several different stages which are fundamental in microarchitecture designs.[4] Some of these stages include instruction fetch, instruction decode, execute, and write back. Some architectures include other stages such as memory access. The design of pipelines is one of the central microarchitectural tasks. A datapath is a collection of functional units, such as ALUs or multipliers, that perform data processing operations. ... A microcontroller is a computer-on-a-chip optimised to control devices. ...


Execution units are also essential to microarchitecture. Execution units include arithmetic logic units (ALU), floating point units (FPU), load/store units, branch prediction, and SIMD. These units perform the operations or calculations of the processor. The choice of the number of execution units, their latency and throughput is a central microarchitectural design task. The size, latency, throughput and connectivity of memories within the system are also microarchitectural decisions. A typical schematic symbol for an ALU: A & B are operands; R is the output; F is the input from the Control Unit; D is an output status In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. ... A floating point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. ... -1...


System-level design decisions such as whether or not to include peripherals, such as memory controllers, can be considered part of the microarchitectural design process. This includes decisions on the performance-level and connectivity of these peripherals. For an account of the words periphery and peripheral as they are used in biology, sociology, politics, computer hardware, and other fields, see the periphery disambiguation page. ... This article or section does not adequately cite its references or sources. ...


Unlike architectural design, where achieving a specific performance level is the main goal, microarchitectural design pays closer attention to other constraints. Since microarchitecture design decisions directly affect what goes into a system, attention must be paid to such issues as:

  • chip area/cost
  • power consumption
  • logic complexity
  • ease of connectivity
  • manufacturability
  • ease of debugging
  • testability

Micro-Architectural Concepts

In general, all CPUs, single-chip microprocessors or multi-chip implementations run programs by performing the following steps:

  1. read an instruction and decode it
  2. find any associated data that is needed to process the instruction
  3. process the instruction
  4. write the results out

Complicating this simple-looking series of steps is the fact that the memory hierarchy, which includes caching, main memory and non-volatile storage like hard disks, (where the program instructions and data reside) has always been slower than the processor itself. Step (2) often introduces a lengthy (in CPU terms) delay while the data arrives over the computer bus. A considerable amount of research has been put into designs that avoid these delays as much as possible. Over the years, a central goal was to execute more instructions in parallel, thus increasing the effective execution speed of a program. These efforts introduced complicated logic and circuit structures. Initially these techniques could only be implemented on expensive mainframes or supercomputers due to the amount of circuitry needed for these techniques. As semiconductor manufacturing progressed, more and more of these techniques could be implemented on a single semiconductor chip. This article is about the computer term. ... Primary storage is a category of computer storage, often called main memory. ... Typical hard drives of the mid-1990s. ... In computer architecture, a bus is a subsystem that transfers data or power between computer components inside a computer or between computers and typically is controlled by device driver software. ...


See Article Central Processing Unit for a more detailed discussion on operation basics. “CPU” redirects here. ...


See Article History of general purpose CPUs for a more detailed discussion on the development history of CPUs. // Each of the computer designs of the early 1950s was a unique design; there were no upward-compatible machines or computer architectures with multiple, differing implementations. ...


What follows is a survey of micro-architectural techniques that are common in modern CPUs.


Instruction Set choice

The choice of which Instruction Set Architecture to use greatly affects the complexity of implementing high performance devices. Over the years, computer architects have strived to simplify instruction sets, which enables higher performance implementations by allowing designers to spend effort and time on features which improve performance as opposed to spending their energies on the complexity inherent in the instruction set. An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ...


Instruction set design has progressed from CISC, RISC, VLIW, EPIC types. Architectures that are dealing with data parallelism include SIMD and Vectors. A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A very long instruction word or VLIW CPU architectures implement a form of instruction level parallelism. ... Explicitly Parallel Instruction Computing (EPIC) is a computing paradigm that began to be researched in the 1990s. ... Data Parallelism is a form of parallelization of computer code. ... -1... Processor board of a CRAY YMP vector computer A vector processor, or array processor, is a CPU design that is able to run mathematical operations on multiple data elements simultaneously. ...


Instruction pipelining

Main article: instruction pipeline

One of the first, and most powerful, techniques to improve performance is the use of the instruction pipeline. Early processor designs would carry out all of the steps above for one instruction before moving onto the next. Large portions of the circuitry were left idle at any one step; for instance, the instruction decoding circuitry would be idle during execution and so on. Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back) An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their performance. ... Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back) An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their performance. ...


Pipelines improve performance by allowing a number of instructions to work their way through the processor at the same time. In the same basic example, the processor would start to decode (step 1) a new instruction while the last one was waiting for results. This would allow up to four instructions to be "in flight" at one time, making the processor look four times as fast. Although any one instruction takes just as long to complete (there are still four steps) the CPU as a whole "retires" instructions much faster and can be run at a much higher clock speed.


RISC make pipelines smaller and much easier to construct by cleanly separating each stage of the instruction process and making them take the same amount of time — one cycle. The processor as a whole operates in an assembly line fashion, with instructions coming in one side and results out the other. Due to the reduced complexity of the Classic RISC pipeline, the pipelined core and an instruction cache could be placed on the same size die that would otherwise fit the core alone on a CISC design. This was the real reason that RISC was faster. Early designs like the SPARC and MIPS often ran over 10 times as fast as Intel and Motorola CISC solutions at the same clock speed and price. Modern car assembly line. ... The introduction to this article provides insufficient context for those unfamiliar with the subject matter. ... Sun UltraSPARC II Microprocessor Sun UltraSPARC T1 (Niagara 8 Core) SPARC (Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. ... A MIPS R4400 microprocessor made by Toshiba. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... Motorola Inc. ...


Pipelines are by no means limited to RISC designs. By 1986 the top-of-the-line VAX (the 8800) was a heavily pipelined design, slightly predating the first commercial MIPS and SPARC designs. Most modern CPUs (even embedded CPUs) are now pipelined, and microcoded CPUs with no pipelining are seen only in the most area-constrained embedded processors. Large CISC machines, from the VAX 8800 to the modern Pentium 4 and Athlon, are implemented with both microcode and pipelines. Improvements in pipelining and caching are the two major microarchitectural advances that have enabled processor performance to keep pace with the circuit technology on which they are based.


Cache

It was not long before improvements in chip manufacturing allowed for even more circuitry to be placed on the die, and designers started looking for ways to use it. One of the most common was to add an ever-increasing amount of cache memory on-die. Cache is simply very fast memory, memory that can be accessed in a few cycles as opposed to "many" needed to talk to main memory. The CPU includes a cache controller which automates reading and writing from the cache, if the data is already in the cache it simply "appears," whereas if it is not the processor is "stalled" while the cache controller reads it in. Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ...


RISC designs started adding cache in the mid-to-late 1980s, often only 4 KB in total. This number grew over time, and typical CPUs now have about 512 KB, while more powerful CPUs come with 1 or 2 or even 4 or 8 MB, organized in multiple levels of a memory hierarchy. Generally speaking, more cache means more speed. The hierarchical arrangement of storage in current computer architectures is called the memory hierarchy. ...


Caches and pipelines were a perfect match for each other. Previously, it didn't make much sense to build a pipeline that could run faster than the access latency of off-chip memory. Using on-chip cache memory instead, meant that a pipeline could run at the speed of the cache access latency, a much smaller length of time. This allowed the operating frequencies of processors to increase at a much faster rate than that of off-chip memory.


Branch Prediction

One of barriers to achieving higher performance through instruction-level parallelism are pipeline stalls and flushes due to branches. Normally, whether a conditional branch will be taken isn't known until late in the pipeline as conditional branches depend on results coming from a register. From the time that the processor's instruction decoder has figured out that it has encountered a conditional branch instruction to the time that the deciding register value can be read out, the pipeline might be stalled for several cycles. On average, every fifth instruction executed is a branch, so that's a high amount of stalling. If the branch is taken, its even worse, as then all of the subsequent instructions which were in the pipeline needs to be flushed.


Techniques such as branch prediction and speculative execution are used to lessen these branch penalties. Branch prediction is where the hardware makes educated guesses on whether a particular branch will be taken. The guess allows the hardware to prefetch instructions without waiting for the register read. Speculative execution is a further enhancement in which the code along the predicted path is executed before it is known whether the branch should be taken or not. In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ... In computer science, speculative execution is the execution of code whose result may not actually be needed. ...


Superscalar

Even with all of the added complexity and gates needed to support the concepts outlined above, improvements in semiconductor manufacturing soon allowed even more logic gates to be used.


In the outline above the processor processes parts of a single instruction at a time. Computer programs could be executed faster if multiple instructions were processed simultaneously. This is what superscalar processors achieve, by replicating functional units such as ALUs. The replication of functional units was only made possible when the die area of a single-issue processor no longer stretched the limits of what could be reliably manufactured. By the late 1980s, superscalar designs started to enter the market place. Simple superscalar pipeline. ...


In modern designs it is common to find two load units, one store (many instructions have no results to store), two or more integer math units, two or more floating point units, and often a SIMD unit of some sort. The instruction issue logic grows in complexity by reading in a huge list of instructions from memory and handing them off to the different execution units that are idle at that point. The results are then collected and re-ordered at the end.-1...


Out-of-order execution

The addition of caches reduces the frequency or duration of stalls due to waiting for data to be fetched from the memory hierarchy, but does not get rid of these stalls entirely. In early designs a cache miss would force the cache controller to stall the processor and wait. Of course there may be some other instruction in the program whose data is available in the cache at that point. Out-of-order execution allows that ready instruction to be processed while an older instruction waits on the cache, then re-orders the results to make it appear that everything happened in the programmed order. In computer engineering, out-of-order execution, OoOE, is a paradigm used in most high-performance microprocessors in order to make use of cycles that would otherwise be wasted by a certain type of costly delay. ...


Speculative execution

One problem with an instruction pipeline is that there are a class of instructions that must make their way entirely through the pipeline before execution can continue. In particular, conditional branches need to know the result of some prior instruction before "which side" of the branch to run is known. For instance, an instruction that says "if x is larger than 5 then do this, otherwise do that" will have to wait for the results of x to be known before it knows if the instructions for this or that can be fetched.


For a small four-deep pipeline this means a delay of up to three cycles — the decode can still happen. But as clock speeds increase the depth of the pipeline increases with it, and modern processors may have 20 stages or more. In this case the CPU is being stalled for the vast majority of its cycles every time one of these instructions is encountered.


The solution, or one of them, is speculative execution, also known as branch prediction. In reality one side or the other of the branch will be called much more often than the other, so it is often correct to simply go ahead and say "x will likely be smaller than five, start processing that". If the prediction turns out to be correct, a huge amount of time will be saved. Modern designs have rather complex prediction systems, which watch the results of past branches to predict the future with greater accuracy. In computer science, speculative execution is the execution of code whose result may not actually be needed. ... In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ...


Multiprocessing and multithreading

Computer architects have become stymied by the growing mismatch in CPU operating frequencies and DRAM access times. None of the techniques that exploited instruction-level parallelism within one program could make up for the long stalls that occurred when data had to be fetched from main memory. Additionally, the large transistor counts and high operating frequencies needed for the more advanced ILP techniques required power dissipation levels that could no longer be cheaply cooled. For these reasons, newer generations of computers have started to exploit higher levels of parallelism that exist outside of a single program or program thread. Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. ... For the form of code consisting entirely of subroutine calls, see Threaded code. ...


This trend is sometimes known as throughput computing. This idea originated in the mainframe market where online transaction processing emphasized not just the execution speed of one transaction, but the capacity to deal with massive numbers of transactions. With transaction-based applications such as network routing and web-site serving greatly increasing in the last decade, the computer industry has re-emphasized capacity and throughput issues. OLTP (Online Transaction Processing) is a form of transaction processing conducted via computer network. ...


One technique of how this parallelism is achieved is through multiprocessing systems, computer systems with multiple CPUs. Once reserved for high-end mainframes and supercomputers, small scale (2-8) multiprocessors servers have become commonplace for the small business market. For large corporations, large scale (16-256) multiprocessors are common. Even personal computers with multiple CPUs have appeared since the 1990s. Multiprocessing is traditionally known as the use of multiple concurrent processes in a system as opposed to a single process at any one instant. ... For other uses, see Mainframe. ... A supercomputer is a computer that led the world (or was close to doing so) in terms of processing capacity, particularly speed of calculation, at the time of its introduction. ...


With further transistor size reductions made available with semiconductor technology advances, multicore CPUs have appeared where multiple CPUs are implemented on the same silicon chip. Initially used in chips targeting embedded markets, where simpler and smaller CPUs would allow multiple instantiations to fit on one piece of silicon. By 2005, semiconductor technology allowed dual high-end desktop CPUs CMP chips to be manufactured in volume. Some designs, such as Sun Microsystems' UltraSPARC T1 have reverted back to simpler (scalar, in-order) designs in order to fit more processors on one piece of silicon. Diagram of an Intel Core 2 dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache. ... Sun Microsystems, Inc. ... Sun Microsystems UltraSPARC T1 microprocessor, known until its 14 November 2005 announcement by its development codename Niagara , is a multithreading, multicore CPU. Designed to lower the energy consumption of server computers, the CPU uses typically 72 W of power at 1. ...


Another technique that has become more popular recently is multithreading. In multithreading, when the processor has to fetch data from slow system memory, instead of stalling for the data to arrive, the processor switches to another program or program thread which is ready to execute. Though this does not speed up a particular program/thread, it increases the overall system throughput by reducing the time the CPU is idle. Many programming languages, operating systems, and other software development environments support what are called threads of execution. ...


Conceptually, multithreading is equivalent to a context switch at the operating system level. The difference is that a multithreaded CPU can do a thread switch in one CPU cycle instead of the hundreds or thousands of CPU cycles a context switch normally requires. This is achieved by replicating the state hardware (such as the register file and program counter) for each active thread. A context switch is the computing process of storing and restoring the state (context) of a CPU such that multiple processes can share a single CPU resource. ... A register file is an array of processor registers in a central processing unit (CPU). ... The program counter (also called the instruction pointer in some computers) is a register in a computer processor which indicates where the computer is in its instruction sequence. ...


A further enhancement is simultaneous multithreading. This technique allows superscalar CPUs to execute instructions from different programs/threads simultaneously in the same cycle. Simultaneous multithreading, often abbreviated as SMT, is a technique for improving the overall efficiency of superscalar CPUs. ...


See Article History of general purpose CPUs for other research topics affecting CPU design. // Each of the computer designs of the early 1950s was a unique design; there were no upward-compatible machines or computer architectures with multiple, differing implementations. ...


See also

A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... It has been suggested that this article or section be merged with embedded microprocessor. ... A digital signal processor (DSP) is a specialized microprocessor designed specifically for digital signal processing, generally in real-time. ... CPU design is the hardware design of a central processing unit. ... In electronics, a hardware description language or HDL is any language from a class of computer languages for formal description of electronic circuits. ... Hardware is an expression used within the engineering disciplines to explicitly distinguish the (electronic computer) hardware from the software which runs in it. ... The term Harvard architecture originally referred to computer architectures that used physically separate storage and signal pathways for their instructions and data (in contrast to the von Neumann architecture). ... Design of the Von Neumann architecture For the robotic architecture also named after Von Neumann, see Von Neumann machine The von Neumann architecture is a computer design model that uses a single storage structure to hold both instructions and data. ... Diagram of an Intel Core 2 dual core processor, with CPU-local Level 1 caches, and a shared, on-die Level 2 cache. ... A datapath is a collection of functional units, such as ALUs or multipliers, that perform data processing operations. ... Dataflow architecture is a computer architecture that directly contrasts the traditional von Neuman or control flow architecture. ... VLSI may refer to: Very-large-scale integration, a process for the creation of electronic integrated circuits VLSI Technology (1979–1999), a former American integrated circuit manufacturer, now a part of Philips Electronics VLSI Solution, a Finnish integrated circuit manufacturer Category: ... VHDL, or VHSIC Hardware Description Language, is commonly used as a design-entry language for field-programmable gate arrays and application-specific integrated circuits in electronic design automation of digital circuits. ... Verilog is a hardware description language (HDL) used to model electronic systems. ... For other uses, see Event Stream Processing. ...

References

  1. ^ Phillip A. Laplante (2001). Dictionary of Computer Science, Engineering, and Technology. CRC Press, 94–95. ISBN 0849326915. 
  2. ^ William F. Gilreath and Phillip A. Laplante (2003). Computer Architecture: A Minimalist Perspective. Springer, 5. ISBN 1402074166. 
  3. ^ Sivarama P. Dandamudi (2003). Fundamentals of Computer Organization and Design. Springer, 5. ISBN 038795211X. 
  4. ^ a b John L. Hennessy and David A. Patterson (2003). Computer Architecture: A Quantitative Approach, Third Edition, Morgan Kaufmann Publishers, Inc. ISBN 1558605967. 

Year 2003 (MMIII) was a common year starting on Wednesday of the Gregorian calendar. ...

Further reading

  • D. Patterson and J. Hennessy (2004-08-02). Computer Organization and Design: The Hardware/Software Interface. Morgan Kaufmann Publishers, Inc.. ISBN 1558606041. 
  • V. C. Hamacher, Z. G. Vrasenic, and S. G. Zaky (2001-08-02). Computer Organization. McGraw-Hill. ISBN 0072320869. 
  • William Stallings (2002-07-15). Computer Organization and Architecture. Prentice Hall. ISBN 0130351199. 
  • J. P. Hayes (2002-09-03). Computer Architecture and Organization. ISBN 0072861983. 
  • Gary Michael Schneider (1985). The Principles of Computer Organization. Wiley, 6–7. ISBN 0471885525. 
  • M. Morris Mano (1992-10-19). Computer System Architecture. Prentice Hall, 3. ISBN 0131755633. 
  • Mostafa Abd-El-Barr and Hesham El-Rewini (2004-12-03). Fundamentals of Computer Organization and Architecture. Wiley-Interscience, 1. ISBN 0471467413. 
  • IEEE Computer Society
  • PC Processor Microarchitecture

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