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Encyclopedia > Memory management unit
This 68451 MMU could be used with the Motorola 68010
This 68451 MMU could be used with the Motorola 68010

MMU, short for memory management unit or sometimes called paged memory management unit as PMMU, is a class of computer hardware components responsible for handling memory accesses requested by the CPU. Among the functions of such devices are the translation of virtual addresses to physical addresses (i.e., virtual memory management), memory protection, cache control, bus arbitration, and, in simpler computer architectures (especially 8-bit systems), bank switching. Image File history File linksMetadata Size of this preview: 800 × 600 pixel Image in higher resolution (2560 × 1920 pixel, file size: 1. ... Image File history File linksMetadata Size of this preview: 800 × 600 pixel Image in higher resolution (2560 × 1920 pixel, file size: 1. ... The Motorola MC68010 processor is a 16/32-bit microprocessor from Motorola, released in 1982 [1]. It is largely similar to the Motorola 68000 CPU with the exception of the addition of several instructions for breakpoint and register control (ccr instead of sr), as well as the ability to save... Computer hardware is the physical part of a computer, including the digital circuitry, as distinguished from the computer software that executes within the hardware. ... The terms storage (U.K.) or memory (U.S.) refer to the parts of a digital computer that retain physical state (data) for some interval of time, possibly even after electrical power to the computer is turned off. ... Die of an Intel 80486DX2 microprocessor (actual size: 12×6. ... Virtual address In computer terminology a virtual address is an address not identifying a logical interface or device, but to a virtual (not physical) entity. ... In computer science, a physical address is the address presented to a computers main memory in a virtual memory system, in contrast to the virtual address which is the address generated by the CPU. Virtual addresses are translated into physical addresses by a memory management unit (abbreviated MMU). ... It has been suggested that this article be split into multiple articles. ... Memory protection is a system that prevents one process from corrupting the memory of another process running on the same computer at the same time. ... Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ... In computer architecture, a bus is a subsystem that transfers data or power between computer components inside a computer or between computers and typically is controlled by device driver software. ... Arbiters are used in asynchronous circuits to order computational activities for shared resources to preventing concurrent incorrect operations. ... 8-bit refers to the number of bits used in the data bus of a computer. ... Bank switching (also known as paging, but only loosely related to the ordinary meaning of paging in computing) was a technique common in 8-bit microcomputer systems, to increase the amount of addressable RAM and ROM without extending the address bus. ...


Modern MMUs typically divide the virtual address space (the range of addresses used by the processor) into pages, whose size is 2N, usually a few kibibytes. The bottom n bits of the address (the offset within a page) are left unchanged. The upper address bits are the (virtual) page number. The MMU normally translates virtual page numbers to physical page numbers via an associative cache called a Translation Lookaside Buffer (TLB). When the TLB lacks a translation, a slower mechanism involving hardware-specific data structures or software assistance will be used. The data items found in such data structures are typically called page table entries (PTEs), and the data structure itself is typically called a page table. The physical page number is combined with the page offset to give the complete physical address. The introduction to this article provides insufficient context for those unfamiliar with the subject matter. ... Alternate meanings: See paging (telecommunications). ... A kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage, commonly abbreviated KiB (never kiB). 1 kibibyte = 210 bytes = 1,024 bytes The kibibyte is closely related to the kilobyte, which can be used either as a synonym for kibibyte or to refer to... A Translation Lookaside Buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translation. ... Relationship between pages addressed by virtual addresses and the frames in physical memory, within a simple address space scheme. ...


A PTE or TLB entry may also include information about whether the page has been written to (the dirty bit), when it was last used (the accessed bit, for a least recently used page replacement algorithm), what kind of processes (user mode, supervisor mode) may read and write it, and whether it should be cached. Cache algorithms are optimizing instructions â€“ algorithms â€“ that a computer program can follow to manage a cache of information stored on the computer. ... In a computer operating system which utilises paging for virtual memory memory management, page replacement algorithms decide what pages to page out (swap out) when a page needs to be allocated. ... User mode refers to two similar concepts in computer architecture. ... In computer terms, supervisor mode is a hardware-mediated flag which can be changed by code running in system-level software. ... Look up cache in Wiktionary, the free dictionary. ...


It is possible that a TLB entry or PTE prohibits access to a virtual page, perhaps because no physical memory (RAM) has been allocated to that virtual page. In this case the MMU will signal a page fault to the CPU. The operating system will then handle the situation appropriately, perhaps by trying to find a spare page of RAM and set up a new PTE to map it to the requested virtual address. If no RAM is free it may be necessary to choose an existing page, using some replacement algorithm, and save it to disk (this is known as "paging"). With some MMUs there can also be a shortage of PTEs or TLB entries, in which case the OS will have to free one for the new mapping. Random Access Memory (usually known by its acronym, RAM) is a type of data storage used in computers. ... In computer storage technology, a page fault is an interrupt (or exception) to the software raised by the hardware, when a program accesses a page that is not mapped in physical memory. ... An operating system (OS) is a computer program that manages the hardware and software resources of a computer. ... In computer operating systems, paging memory allocation, paging refers to the process of managing program access to virtual memory pages that do not currently reside in RAM. It is implemented as a task that resides in the kernel of the operating system and gains control when a page fault takes...


In some cases a "page fault" may indicate a software bug. A key benefit of an MMU is memory protection: an operating system can use it to protect against errant programs, by disallowing access to memory that a particular program should not have access to. Typically, an operating system assigns each program its own virtual address space. Memory protection is a system that prevents one process from corrupting the memory of another process running on the same computer at the same time. ... An operating system (OS) is a computer program that manages the hardware and software resources of a computer. ...


An MMU also reduces the problem of fragmentation of memory. After blocks of memory have been allocated and freed, the free memory may become fragmented (discontinuous) so that the largest contiguous block of free memory may be much smaller than the total amount. With virtual memory, a contiguous range of virtual addresses can be mapped to several non-contiguous blocks of physical memory. Fragmentation is a term that occurs in several fields and describes a process of something breaking or being divided into pieces (fragments). ...


In early designs memory management was performed by a separate integrated circuit such as the MC 68851 used with the Motorola 68020 CPU in the Macintosh II or the Z8015 used with the Zilog Z80 family of processors. Later CPUs such as the Motorola 68030 and the ZILOG Z280 have MMUs on the same IC as the CPU. Integrated circuit showing memory blocks, logic and input/output pads around the periphery Microchips with a transparent window showing the integrated circuit inside. ... Motorola 68020 The Motorola 68020 is a microprocessor from Motorola. ... Macintosh II was the first personal computer model of the Macintosh II series in the Apple Macintosh line. ... One of the first Z80 microprocessors manufactured; the date stamp says well before July 1976. ... Motorola 68030 Processor from a Macintosh IIsi The Motorola 68030 is a 32-bit microprocessor in Motorolas 68000 family. ... The Z280 is a Zilog 16 bit, Z80 compatible processor from 1987. ...


While this article concentrates on modern MMUs, which almost invariably use paging, other systems like segmentation and base-limit addressing (of which the former is a development) have been used in MMUs and are occasionally still present on modern architectures; perhaps most notably, the x86 ISA provides for segmentation in addition to paging. In computer operating systems, paging memory allocation, paging refers to the process of managing program access to virtual memory pages that do not currently reside in RAM. It is implemented as a task that resides in the kernel of the operating system and gains control when a page fault takes... Segmentation is one of the most common ways to achieve memory protection; another common one is paging. ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... An instruction set, or instruction set architecture (ISA), describes the aspects of a computer architecture visible to a programmer, including the native datatypes, instructions, registers, addressing modes, memory architecture, interrupt and exception handling, and external I/O (if any). ...


Examples

Most modern systems divide memory into pages that are 4 KiB to 64 KiB in size, often with the possibility to use huge pages from 2 MiB to 512 MiB in size. Page translations are cached in a TLB. Some systems, mainly older RISC designs, trap into the OS when a page translation is not found in the TLB. Most systems use a hardware-based tree walker. Most systems allow the MMU to be disabled; some will disable the MMU when trapping into OS code. According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... The three-letter acronym MIB may refer to any of several concepts: Management information base, a computing information repository used (for example) by SNMP In marbles, any marble, but esp. ... A Translation Lookaside Buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translation. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ...

DEC Alpha
The Alpha processor divides memory into 8192-byte pages. After a TLB miss, low-level firmware machine code (here called PALcode) walks a 3-level tree-structured page table. Addresses are broken down as follows: 21 bits unused, 10 bits to index the root level of the tree, 10 bits to index the middle level of the tree, 10 bits to index the leaf level of the tree, and 13 bits that pass through to the physical address without modification. Full read/write/execute permission bits are supported.
PowerPC G1, G2, G3, and G4
Pages are normally 4 KiB. After a TLB miss, the standard PowerPC MMU begins two simultaneous lookups. One lookup attempts to match the address with one of 4 or 8 data Block Address Translation (BAT) registers, or 4 or 8 code BAT registers as appropriate. The BAT registers can map linear chunks of memory as large as 256 MiB, and are normally used by an OS to map large portions of the address space for the OS kernel's own use. If the BAT lookup succeeds, the other lookup will be halted and ignored. The other lookup, not directly supported by all processors in this family, is via a so-called "inverted page table" which acts as a hashed off-chip extension of the TLB. First, the top 4 bits of the address are used to select one of 16 segment registers. 24 bits from the segment register replace those 4 bits, producing a 52-bit address. The use of segment registers allows multiple processes to share the same hash table. The 52-bit address is hashed, then used as an index into the off-chip table. There, a group of 8 page table entries will be scanned for one that matches. If none match due to excessive hash collisions, the processor will try again with a slightly different hash function. If this too fails, the CPU will trap into the OS (with MMU disabled) so that the problem may be resolved. The OS will need to discard an entry from the hash table to make room for a new entry. The OS may generate the new entry from a more-normal tree-like page table or from per-mapping data structures which are likely to be slower and more space-efficient. Support for no-execute control is in the segment registers, leading to 256-MiB granularity. One of the major problems with this design is poor cache locality caused by the hash function. Tree-based designs avoid this problem by placing the page table entries for adjacent pages in adjacent locations. An operating system running on the PowerPC may minimize the size of the hash table to reduce this problem. It is also somewhat slow to remove the page table entries of a process; the OS may avoid reusing segment values to delay facing this or it may elect to suffer the waste of memory associated with per-process hash tables. G1 chips do not search for page table entries, but they do generate the hash with the expectation that an OS will search the standard hash table via software. (the OS can write to the TLB) G2, G3, and early G4 chips use hardware to search the hash table. The latest chips allow the OS to choose either method. On chips that make this optional or do not support it at all, the OS may choose to use a tree-based page table exclusively.
VAX
Pages are 512 bytes, which is very small. An OS may treat multiple pages as if they were a single larger page. Linux groups 8 pages together so that the system can be viewed as having 4 KiB pages. The VAX divides memory into 4 fixed-purpose regions, each 1 GiB in size. They are: paged memory for applications, paged memory for the kernel, unpaged memory for the kernel, and unused. Page tables are big linear arrays. Normally this would be very wasteful when addresses are used at both ends of the possible range, but the page table for applications is itself stored in the kernel's paged memory. Thus there is effectively a 2-level tree, allowing applications to have sparse memory layout without wasting lots of space on unused page table entries. The VAX MMU is notable for lacking an accessed bit. OSes which implement paging must find some way to emulate the accessed bit if they are to operate efficiently. Typically, the OS will periodically unmap pages so that page-not-present faults can be used to let the OS set an accessed bit.
x86
The x86 architecture has evolved over a long period of time while maintaining full software compatibility even for OS code. The MMU is thus extremely complex, with many different possible operating modes. Normal operation of the traditional 80386 CPU and its successors is described here. The CPU primarily divides memory into 4 KiB pages. Segment registers, fundamental to the older 8088 and 80286 MMU designs, are avoided as much as possible by modern OSes. There is one major exception to this: access to thread-specific data for applications or CPU-specific data for OS kernels, which is done with explicit use of the FS and GS segment registers. All memory access involves a segment register, chosen according to the code being executed. The segment register acts as an index into a table, which provides an offset to be added to the virtual address. Except when using FS or GS as described above, the OS ensures that the offset will be zero. After the offset is added, the address is masked to be no larger than 32 bits. The result may be looked up via a tree-structured page table, with the bits of the address being split as follows: 10 bits for the root of the tree, 10 bits for the leaves of the tree, and the 12 lowest bits being directly copied to the result. No-execute support is only provided on a per-segment basis, making it very awkward to use. PaX is one way to emulate per-page non-execute support via the segments, with minor performance loss and the loss of half of the available address space. Minor revisions of the MMU introduced with the Pentium have allowed huge 2 MiB or 4 MiB pages by skipping the bottom level of the tree. Minor revisions of the MMU introduced with the Pentium Pro have allowed 36-bit physical addresses and specification of cachability by looking up a few high bits in a small on-CPU table.
x86-64
x86-64 is a 64-bit extension of x86, and thus is very similar. 64-bit usage, called long mode, will be described here. Excepting FS and GS, all segment offsets are ignored. The page table tree has four levels. The virtual addresses are divided up as follows: 16 bits unused, 9 bits each for 4 tree levels (total: 36 bits) , and the 12 lowest bits unmodified. The 16 highest bits are required to match the next highest bit; the low 48 bits are sign extended to fill the high 16 bits. A per-page no-execute bit, called the NX bit, can be used to block execution of individual pages.
IBM System/370 and successors
The S/370 and its successors System/390 and z/Architecture have the unusual feature of storing accessed and dirty bits outside of the page table. They refer to physical memory rather than virtual memory. They are accessed by special-purpose instructions. These unusual features make virtualization easier. They also reduce overhead for the OS, which would otherwise need to propagate accessed and dirty bits from the page tables to a more physically-oriented data structure.


This article was originally based on material from the Free On-line Dictionary of Computing, which is licensed under the GFDL. DEC Alpha AXP 21064 Microprocessor The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp (DEC). ... In computing, on the DEC Alpha microprocessor, PALcode (Privileged Architecture Library code) is the name used by DEC for a set of functions in the SRM or AlphaBIOS firmware, providing a hardware abstraction layer for system software, covering features such as cache management, translation lookaside buffer (TLB) miss handling, interrupt... IBM PowerPC 601 Microprocessor PowerPC is a RISC microprocessor architecture created by the 1991 Apple–IBM–Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ... According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... The three-letter acronym MIB may refer to any of several concepts: Management information base, a computing information repository used (for example) by SNMP In marbles, any marble, but esp. ... Relationship between pages addressed by virtual addresses and the frames in physical memory, within a simple address space scheme. ... Segmentation is one of the most common ways to achieve memory protection; another common one is paging. ... In computer science, a hash collision is a situation that occurs when two distinct inputs into a hash function produce identical outputs. ... A hash function (or hash algorithm) is a reproducible method of turning data (usually a message or a file) into a number suitable to be handled by a computer. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (aka code) or for storage of data, a feature normally only found in Harvard architecture processors. ... VAX is a 32-bit computing architecture that supports an orthogonal instruction set (machine language) and virtual addressing (i. ... The term gib may refer to: a castrated male cat or ferret an abbreviation for gibibyte (GiB) or gibibit (Gib) an abbreviation for Gibraltar an abbreviation for Gib Board, itself an abbreviation of Gibraltar Board, all Winston Wallboards[1] tradenames for drywall (plasterboard). ... x86 or 80x86 is the generic name of a microprocessor architecture first developed and manufactured by Intel. ... The Intel 80386 is a microprocessor which was used as the central processing unit (CPU) of many personal computers from 1986 until 1994 and later. ... The Intel 8088 is an Intel microprocessor based on the 8086, with 16-bit registers and an 8-bit external data bus. ... The Intel 80286 is an x86-family 16-bit microprocessor that was introduced by Intel on February 1, 1982. ... A thread in computer science is short for a thread of execution. ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (aka code) or for storage of data, a feature normally only found in Harvard architecture processors. ... In computer security, PaX is a patch for the Linux kernel that implements least privilege protections for memory pages. ... Pentium logo, with MMX enhancement The Pentium is a fifth-generation x86 architecture microprocessor from Intel. ... Pentium Pro 256 KB Pentium Pro 512 KB Pentium Pro 1 MB Pentium Pro underside (256/512) Pentium II Overdrive The Pentium Pro is a sixth-generation x86 architecture microprocessor (P6 core) by Intel originally intended to replace the original Pentium in a full range of applications, but later reduced... The AMD64 or x86-64 is a 64-bit processor architecture invented by AMD. It is a superset of the x86 architecture, which it natively supports. ... In the x86-64 CPU architecture Long mode, is the mode where an application (or operating system) can access the 64-bit instructions and registers, while 32-bit programs are executed in a compatibility mode. ... Sign extension is the operation, in computer arithmetic, of increasing the number of bits of a binary number while preserving the numbers sign (positive/negative). ... The NX bit, which stands for No eXecute, is a technology used in CPUs to segregate areas of memory for use by either storage of processor instructions (aka code) or for storage of data, a feature normally only found in Harvard architecture processors. ... The IBM System/370 (often: S/370) was a model range of IBM mainframes announced on June 30, 1970 as the successors to the System/360 family. ... The title given to this article is incorrect due to technical limitations. ... z/Architecture (formerly known as ESAME) refers to IBMs 64-bit computing architecture for its top-of-the-line enterprise servers. ... In computing, virtualization is a broad term that refers to the abstraction of computer resources. ... The Free On-line Dictionary of Computing (FOLDOC) is an online, searchable encyclopedic dictionary of computing subjects. ... GNU logo (similar in appearance to a gnu) The GNU Free Documentation License (GNU FDL or simply GFDL) is a copyleft license for free content, designed by the Free Software Foundation (FSF) for the GNU project. ...


  Results from FactBites:
 
U.S. Patent: 5293597 - Concurrent context memory management unit - March 8, 1994 (2939 words)
The memory management unit set forth in claim 1 wherein said memory management unit is interposed between a central processing unit (CPU) and said memory and wherein said storage or retrieval instructions are received from said CPU, and wherein said plurality of sources includes a plurality of processes operating within said CPU.
The memory management unit set forth in claim 1 wherein in a default mode said selecting means includes means for selecting a particular one of said stored sets of translation information as a function of the source of said received instruction but independent of whether it is a read instruction or a write instruction.
MMU 40 then consults the virtual address table located in memory 42 for the current process (whose ID was loaded into MMU 40 earlier by CPU 41) and determines the translation and permission access for this virtual address.
Memory management unit - Wikipedia, the free encyclopedia (1924 words)
MMU, short for memory management unit, is a class of computer hardware components responsible for handling memory accesses requested by the CPU.
A key benefit of an MMU is memory protection: an operating system can use it to protect against errant programs, by disallowing access to memory that a particular program should not have access to.
In early designs memory management was performed by a separate integrated circuit such as the MC 68851 used with the Motorola 68020 CPU in the Macintosh II or the Z8015 used with the Zilog Z80 family of processors.
  More results at FactBites »

 
 

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