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Encyclopedia > MIPS architecture
A MIPS R4400 microprocessor made by Toshiba.

MIPS, for Microprocessor without Interlocked Pipeline Stages, is a RISC microprocessor architecture developed by MIPS Technologies. By the late 1990s it was estimated that one in three RISC chips produced were MIPS-based designs.[citation needed] Download high resolution version (798x798, 43 KB) Wikipedia does not have an article with this exact name. ... Download high resolution version (798x798, 43 KB) Wikipedia does not have an article with this exact name. ... Toshiba Corporations headquarters (Center) in Hamamatsucho, Tokyo Toshiba Corporation sales by division for year ending March, 31 2005 Toshiba Corporation ) (TYO: 6502 ) is a multinational high technology electrical and electronics manufacturing firm, headquartered in Tokyo, Japan. ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... MIPS Technologies, formerly MIPS Computer Systems, is most widely known for developing the MIPS architecture and a series of pioneering RISC CPUs. ... For the album by Prince, see 1999 (album) 1999 is a common year starting on Friday of the Gregorian calendar, and was designated the International Year of Older Persons by the United Nations. ...

MIPS designs are used in many embedded systems such as the Series2 TiVo, Windows CE devices, Cisco routers, and video game consoles like the Nintendo 64 and Sony PlayStation, PlayStation 2, and PlayStation Portable handheld system. Until late 2006 they were also used in many of SGI's computer products. It has been suggested that Embedded System Design in an FPGA be merged into this article or section. ... TiVo (pronounced tee-voh, IPA: ) is a popular brand of digital video recorder (DVR) in the United States. ... Windows CE (sometimes abbreviated WinCE) is a variation of Microsofts Windows operating system for minimalistic computers and embedded systems. ... A Cisco ASM/2-32EM router deployed at CERN in 1987. ... Cisco 1800 Router ERS-8600 In simple layman terms, a router is a device that determines the proper path for data to travel between different networks. ... A video game console is an interactive entertainment computer or electronic device that manipulates the video display signal of a display device (a television, monitor, etc. ... This section needs additional references or sources to facilitate its verification. ... Sony Corporation ) is a Japanese multinational corporation and one of the worlds largest media conglomerates with revenue of \$68. ... The Sony PlayStation ) is a video game console of the 32/64-bit era, first produced by Sony Computer Entertainment in the mid-1990s. ... The PlayStation 2 , abbreviated PS2) is Sonys second video game console, the successor to the PlayStation and the predecessor to the PlayStation 3. ... The PlayStation Portable , officially abbreviated as PSP) is a handheld game console released and currently manufactured by Sony Computer Entertainment. ... Silicon Graphics, Inc. ...

Because the designers created such a clean instruction set, computer architecture courses in universities and technical schools often study the MIPS architecture. The design of the MIPS CPU family greatly influenced later RISC architectures such as DEC Alpha. A typical vision of a computer architecture as a series of abstraction layers: hardware, firmware, assembler, kernel, operating system and applications (see also Tanenbaum 79). ... Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... DEC Alpha AXP 21064 Microprocessor die photo Package for DEC Alpha AXP 21064 Microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp...

### RISC Pioneer

In 1981, a team led by John L. Hennessy at Stanford University started work on what would become the first MIPS processor. The basic concept was to dramatically increase performance through the use of deep instruction pipelines, a technique that was well known, but difficult to implement. Generally in a pipeline architecture, successive instructions in a program sequence will overlap in execution. Modules inside CPU work in parallel so that CPU will load and start executing an instruction before the preceding instruction is complete. In contrast, traditional designs of the era waited to complete an entire instruction before moving on, thereby leaving large areas of the CPU idle as the process continued. Moreover, the clock frequency of the whole CPU was dictated by the latency of the entire instruction cycle, rather than by the critical path (i.e. the latency of the pipeline stage taking the longest time to complete). Year 1981 (MCMLXXXI) was a common year starting on Thursday (link displays the 1981 Gregorian calendar). ... John LeRoy Hennessy, the founder of MIPS Computer Systems Inc. ... Leland Stanford Junior University, commonly known as Stanford University (or simply Stanford), is a private university located approximately 37 miles (60 kilometers) southeast of San Francisco and approximately 20 miles northwest of San JosÃ© in Stanford, California. ... Basic five-stage pipeline in a RISC machine (IF = Instruction Fetch, ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back) An instruction pipeline is a technique used in the design of computers and other digital electronic devices to increase their performance. ... In synchronous digital electronics, such as most computers, a clock signal is a signal used to coordinate the actions of two or more circuits. ... The instruction cycle is the time period during which one instruction is fetched from memory and executed when a computer is given an instruction in machine language. ...

One major barrier to pipelining was that it required interlocks to be set up to ensure that instructions that took multiple clock cycles to complete would stop the pipeline from loading more data — basically to pause while it completed. These interlocks can take a long time to set up, and were thought to be a major barrier to future speed improvements. A major aspect of the MIPS design was to demand that all instructions take only one cycle to complete, thereby removing any needs for interlocking.

Although this design eliminated a number of useful instructions, notably things like multiply and divide which would take multiple steps, it was felt that the overall performance of the system would be dramatically improved because the chips could run at much higher clock rates. This ramping of the speed would be difficult with interlocking involved, as the time needed to set up locks is as much a function of die size as clock rate: adding the hardware needed might actually slow down the overall speed.

The elimination of these instructions became a contentious point. Many observers claimed the design (and RISC in general) would never live up to its hype. If one simply replaces the complex multiply instruction with many simpler additions, where is the speed increase? This overly-simple analysis ignored the fact that the speed of the design was in the pipelines, not the instructions.

In 1984 Hennessy was convinced of the future commercial potential of the design, and left Stanford to form MIPS Computer Systems. They released their first design, the R2000, in 1985, improving the design as the R3000 in 1988. These 32-bit CPUs formed the basis of their company through the 1980s, used primarily in SGI's series of workstations. These commercial designs deviated from the Stanford academic research by implementing most of the interlocks in hardware, supplying full multiply and divide instructions (among others). Silicon Graphics, Inc. ... Sun SPARCstation 1+, 25 MHz RISC processor from early 1990s A workstation, such as a Unix workstation, RISC workstation or engineering workstation, is a high-end desktop or deskside microcomputer designed for technical applications. ...

In 1991 MIPS released the first 64-bit microprocessor, the R4000. However, MIPS had financial difficulties while bringing it to market. The design was so important to SGI, at the time one of MIPS' few major customers, that SGI bought the company outright in 1992 in order to guarantee the design would not be lost. As a subsidiary of SGI, the company became known as MIPS Technologies. MIPS Technologies, formerly MIPS Computer Systems, is most widely known for developing the MIPS architecture and a series of pioneering RISC CPUs. ...

### Licensable Architecture

In the early 1990s MIPS started licensing their designs to third-party vendors. This proved fairly successful due to the simplicity of the core, which allowed it to be used in a number of applications that would have formerly used much less capable CISC designs of similar gate count and price -- the two are strongly related; the price of a CPU is generally related to the number of gates and the number of external pins. Sun Microsystems attempted to follow their success by licensing their SPARC core, but it has never been anywhere near as successful. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous 68k family. MIPS was so successful that SGI spun-off MIPS Technologies in 1998. Fully half of MIPS' income today comes from licensing their designs, while much of the rest comes from contract design work on cores that will then be produced by third parties. A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... In microprocessor design, gate count refers to the number of transistor switches, or gates, that are needed to implement a design. ... Sun Microsystems, Inc. ... Sun UltraSPARC II Microprocessor Sun UltraSPARC T1 (Niagara 8 Core) SPARC (Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. ... This page is a candidate for speedy deletion, because: it is patent nonsense. ... The Motorola 680x0/0x0/m68k/68k/68K family of CISC microprocessor CPU chips were 32-bit from the start, and were the primary competition for the Intel x86 family of chips in personal computers of the 1980s and early 1990s. ...

Two companies have emerged that specialize in building Multi-core devices using the MIPS architecture. Raza Microelectronics Inc. purchased the product line from failing Sandcraft and later produced devices that contained 8 CPU cores that were targeted at the telecom and networking markets. Cavium Networks, originally a security processor vendor also produced devices with 8 CPU cores for the same markets. Both of these companies designed their cores in-house, just licensing the architecture instead of purchasing cores from MIPS. This article does not cite any references or sources. ... Cavium Networks is a Mountain View, California-based company specializing in MIPS-based network and security processors. ...

### Losing the Desktop

Among the manufacturers which have made computer workstation systems using MIPS processors are SGI, MIPS Computer Systems, Inc., Olivetti, Siemens-Nixdorf, Acer, Digital Equipment Corporation, NEC, and DeskStation. Operating systems ported to the architecture include SGI's IRIX, Microsoft's Windows NT (until v4.0), Windows CE, Linux, BSD, UNIX System V, SINIX and MIPS Computer Systems' own RISC/os. Sun SPARCstation 1+, 25 MHz RISC processor from early 1990s A workstation, such as a Unix workstation, RISC workstation or engineering workstation, is a high-end desktop or deskside microcomputer designed for technical applications. ... Silicon Graphics, Inc. ... ... Olivetti Lettera 22, 1950 Ing. ... Siemens Nixdorf Informationssysteme, AG (SNI) was formed in the mid 1990s by the merger of Nixdorf Computer AG and the Siemens Data Information Services (DIS) division. ... Acer (LSE: ACID) (Traditional Chinese: ) is a Taiwan-based company. ... The DEC logo Digital Equipment Corporation was a pioneering American company in the computer industry. ... NEC Corporation (Jp. ... ... It has been suggested that Maintenance OS be merged into this article or section. ... IRIX is a computer operating system developed by Silicon Graphics, Inc. ... Microsoft Corporation, (NASDAQ: MSFT, HKSE: 4338) is a multinational computer technology corporation with global annual revenue of US\$44. ... Windows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. ... Windows CE (sometimes abbreviated WinCE) is a variation of Microsofts Windows operating system for minimalistic computers and embedded systems. ... Linux (IPA pronunciation: ) is a Unix-like computer operating system. ... BSD redirects here; for other uses see BSD (disambiguation). ... Filiation of Unix and Unix-like systems Unix (officially trademarked as UNIXÂ®) is a computer operating system originally developed in 1969 by a group of AT&T employees at Bell Labs including Ken Thompson, Dennis Ritchie and Douglas McIlroy. ... AT&T UNIX System V was one of the versions of the UNIX operating system. ... SINIX (later renamed to Reliant UNIX) was a version of the Unix operating system from Siemens Nixdorf Informationssysteme. ... RISC/os is an operating system distributed by MIPS Computer Systems, Inc. ...

There was speculation in the early 1990s that MIPS, and other powerful RISC processors would overtake the Intel IA32 architecture. This was encouraged by the support of the first two versions of Microsoft's Windows NT for DEC Alpha, MIPS and PowerPC - and to a lesser extent the Clipper architecture and SPARC. However, as Intel quickly released faster versions of their Pentium class CPUs, Microsoft Windows NT v4.0 dropped support for anything but Intel. With SGI's decision to transition to the Itanium and IA32 architectures, use of MIPS processors on the desktop has now disappeared almost completely[1]. Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... ... Microsoft Corporation, (NASDAQ: MSFT, HKSE: 4338) is a multinational computer technology corporation with global annual revenue of US\$44. ... Windows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. ... DEC Alpha AXP 21064 Microprocessor die photo Package for DEC Alpha AXP 21064 Microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp... PowerPC is a RISC microprocessor architecture created by the 1991 Appleâ€“IBMâ€“Motorola alliance, known as AIM. Originally intended for personal computers, PowerPC CPUs have since become popular embedded and high-performance processors as well. ... The Clipper architecture is a 32-bit RISC-like instruction set architecture designed by Fairchild Semiconductor. ... Sun UltraSPARC II Microprocessor Sun UltraSPARC T1 (Niagara 8 Core) SPARC (Scalable Processor Architecture) is a RISC microprocessor instruction set architecture originally designed in 1985 by Sun Microsystems. ... This article does not cite any references or sources. ... Windows NT is a family of operating systems produced by Microsoft, the first version of which was released in July 1993. ... Itanium 2 logo Old Itanium logo The Itanium is an IA-64 microprocessor developed jointly by Hewlett-Packard and Intel. ... ...

See main article Advanced Computing Environment. The Advanced Computing Environment (ACE) was defined by an industry consortium in the early 1990s to be the next generation commodity computing platform after DOS-based Personal Computers. ...

### Embedded markets

Through the 1990s, the MIPS architecture was widely adopted by the embedded market, including for use in computer networking/telecommunications, video arcade games, home video game consoles, computer printers, digital set-top boxes, digital televisions, DSL and cable modems, and personal digital assistants. â€œComputer Networksâ€ redirects here. ... Telecommunication involves the transmission of signals over a distance for the purpose of communication. ... Centipede by Atari is a typical example of a 1980s era arcade game. ... A video game console is an interactive entertainment computer or electronic device that manipulates the video display signal of a display device (a television, monitor, etc. ... This does not cite any references or sources. ... The term set-top box (STB) describes a device that connects to a television and some external source of signal, and turns the signal into content then displayed on the screen. ... Digital television (DTV) is a telecommunication system for broadcasting and receiving moving pictures and sound by means of digital signals, in contrast to analog signals used by analog (traditional) TV. DTV uses digital modulation data, which is digitally compressed and requires decoding by a specially designed television set, or a... An ADSL modem, also known as a DSL modem, is a device used to connect one or more computers to a phone line, in order to use an ADSL service. ... Motorola Surfboard cable modem A cable modem is a type of modem that provides access to a data signal sent over the cable television infrastructure. ... User with PDA Personal digital assistants (PDAs) are handheld computers that were originally designed as personal organizers, but became much more versatile over the years. ...

The low power-consumption and heat characteristics of embedded MIPS implementations, the wide availability of embedded development tools, and knowledge about the architecture means use of MIPS microprocessors in embedded roles is likely to remain common.

### Synthesizeable Cores for Embedded Markets

In recent years most of the technology used in the various MIPS generations has been offered as IP-cores (building-blocks) for embedded processor designs. Both 32-bit and 64-bit basic cores are offered, known as the 4K and 5K respectively, and the design itself can be licensed as MIPS32 and MIPS64. These cores can be mixed with add-in units such as FPUs, SIMD systems, various input/output devices, etc. In electronic design a semiconductor intellectual property core, IP block, or IP core is a reusable unit of logic, cell, or chip layout design and is also the property of one party. ... This page is a candidate for speedy deletion, because: it is patent nonsense. ... 32-bit is a term applied to processors, and computer architectures which manipulate the address and data in 32-bit chunks. ... In computing, a 64-bit component is one in which data are processed or stored in 64-bit units (words). ... A floating point unit (FPU) is a part of a CPU specially designed to carry out operations on floating point numbers. ... -1...

MIPS cores have been commercially successful, now being used in many consumer and industrial applications. MIPS cores can be found in newer Cisco, Linksys and Mikrotik's routerboard routers, cable modems and ADSL modems, smartcards, laser printer engines, set-top boxes, robots, handheld computers, Sony PlayStation 2 and Sony PlayStation Portable. In cellphone/PDA applications, the MIPS core has been unable to displace the incumbent, competing ARM core. Cisco may refer to: Cisco Systems, a computer networking company Cisco IOS, an internet router operating system CISCO Security Private Limited, a security company in Singapore Commercial and Industrial Security Corporation, a statutory board in Singapore Abbreviation for San Francisco, California Cisco (wine) The Cisco Kid, a fictional character created... A 802. ... Motorola Surfboard cable modem A cable modem is a type of modem that provides access to a data signal sent over the cable television infrastructure. ... Asymmetric Digital Subscriber Line (ADSL) is a form of DSL, a data communications technology that enables faster data transmission over copper telephone lines than a conventional voiceband modem can provide. ... A smart card, or integrated circuit(s) card (ICC), is defined as any integrated circuitry embedded into a flat, plastic body. ... 1993 Apple LaserWriter Pro 630 laser printer A laser printer is a common type of computer printer that rapidly produces high quality text and graphics on plain paper. ... The term set-top box (STB) describes a device that connects to a television and some external source of signal, and turns the signal into content then displayed on the screen. ... ASIMO, a humanoid robot manufactured by Honda. ... The PlayStation 2 , abbreviated PS2) is Sonys second video game console, the successor to the PlayStation and the predecessor to the PlayStation 3. ... The PlayStation Portable , officially abbreviated as PSP) is a handheld game console released and currently manufactured by Sony Computer Entertainment. ... The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit RISC processor architecture developed by ARM Limited that is widely used in a number of embedded designs. ...

Examples of MIPS-powered devices: Broadcom BCM5352E - WiFi router processor with 54g WLAN, fast Ethernet, 200 MHz, 16KiB ins. 8KiB data cache, 256B prefetch cache, MMU, 16-bit 100 MHz SDRAM controller, serial/parallel flash, 5-port 100 Mbit/s Ethernet (switch), 16 GPIO, JTAG, 2xUART, 336-ball BGA. BCM 11xx, 12xx, 14xx - 64bit "SiByte" MIPS line. Broadcom Corporation is a leading American supplier of integrated circuits (ICs) for broadband communications. ... Wi-Fi (or Wi-fi, WiFi, Wifi, wifi), short for Wireless Fidelity, is a set of standards for wireless local area networks (WLAN) currently based on the IEEE 802. ...

MIPS architecture processors include: IDT RC32438; ATI Xilleon; Alchemy Au1000, 1100, 1200; Broadcom Sentry5; RMI XLR7xx, Cavium Octeon CN30xx, CN31xx and CN38xx; Infineon Technologies EasyPort, Amazon, Danube, ADM5120, WildPass, INCA-IP, INCA-IP2; NEC EMMA and EMMA2, NEC VR4181A, VR4121, VR4122, VR4181A, VR5432, VR5500; Oak Technologies Generation; PMC-Sierra RM11200; QuickLogic QuickMIPS ESP; Toshiba "Donau", Toshiba TMPR492x, TX4925, TX9956, TX7901. IDT may refer to: IDT Corp. ... ATI may stand for: ATI Technologies Inc. ... Cavium Networks is a Mountain View, California-based company specializing in MIPS-based network and security processors. ... Infineon Technologies AG (ISIN: DE0006231004, FWB: IFX, NYSE: IFX) was founded in April 1999 when the semiconductor operations of parent company, Siemens AG, were spun off to form a separate legal entity. ... NEC Corporation (Japanese: Nippon Denki Kabushiki Gaisha; TYO: 6701 , NASDAQ: NIPNY) is a Japanese multinational IT company headquartered in Minato-ku, Tokyo, Japan. ... Oak Technologies was founded in 1987. ... PMC-Sierra NASDAQ: PMCS is a fabless semiconductor company which develops and sells devices into the communications, storage, printing, and embedding computing marketplaces. ... Toshiba Corporations headquarters (Center) in Hamamatsucho, Tokyo Toshiba Corporation sales by division for year ending March, 31 2005 Toshiba Corporation ) (TYO: 6502 ) is a multinational high technology electrical and electronics manufacturing firm, headquartered in Tokyo, Japan. ...

## CPU family

Pipeline MIPS

The R2000 could be booted either big-endian or little-endian. It had thirty-two 32-bit general purpose registers, but no condition code register, considering it a potential bottleneck, a feature it shares with the AMD 29000 and the DEC Alpha. Unlike other registers the program counter is not directly accessible. When integers or any other data are represented with multiple bytes, there is no unique way of ordering of those bytes in memory or in a transmission over some medium, and so the order is subject to arbitrary convention. ... When integers or any other data are represented with multiple bytes, there is no unique way of ordering of those bytes in memory or in a transmission over some medium, and so the order is subject to arbitrary convention. ... The Condition Code register, or CCR, is a register which has its bits set or reset when certain conditions are met. ... AMD 29000 Microprocessor The AMD 29000, often simply 29k, was a popular family of RISC-based 32-bit microprocessors and microcontrollers from Advanced Micro Devices. ... DEC Alpha AXP 21064 Microprocessor die photo Package for DEC Alpha AXP 21064 Microprocessor Alpha AXP 21064 bare die mounted on a business card with some statistics The DEC Alpha, also known as the Alpha AXP, is a 64-bit RISC microprocessor originally developed and fabricated by Digital Equipment Corp...

The R2000 also had support for up to four co-processors, one of which was built into the main CPU and handled exceptions, traps and memory management, while the other three were left for other uses. One of these could be filled by the optional R2010 FPU, which had thirty-two 32-bit registers that could be used as sixteen 64-bit registers for double-precision. A floating point unit (FPU) is a part of a computer system specially designed to carry out operations on floating point numbers. ...

The R3000 succeeded the R2000 in 1988, adding 32 kB (soon increased to 64 KB) caches for instructions and data, along with cache coherency support for multi-processor use. While there were flaws in the R3000's multiprocessor support, it still managed to be a part of several successful multiprocessor designs. The R3000 also included a built-in MMU, a common feature on CPUs of the era. The R3000 was the first successful MIPS design in the marketplace, and eventually over 1 million were made. The R3000A, used in the extremely successful Sony PlayStation, was a speed bumped version running at 40 MHz that delivered a performance of 32 VUPs. Like the R2000, the R3000 was paired with the R3010 FPU. Pacemips produced an R3400 and IDT produced R3500, both of them were R3000s with R3010 fpu on a single chip. Toshiba's R3900 was a virtually first SoC for the early Handheld PCs based on the Windows CE. The Mongoose-V is a radiation-hardened and expanded version of the MIPS R3000 CPU paired with an on-chip R3010 FPU used for space applications. Year 1988 (MCMLXXXVIII) was a leap year starting on Friday (link displays 1988 Gregorian calendar). ... Cache coherence refers to the integrity of data stored in local caches of a shared resource. ... This 68451 MMU could be used with the Motorola 68010 MMU, short for memory management unit or sometimes called paged memory management unit as PMMU, is a class of computer hardware components responsible for handling memory accesses requested by the CPU. Among the functions of such devices are the translation... Sony Corporation ) is a Japanese multinational corporation and one of the worlds largest media conglomerates with revenue of \$68. ... The Sony PlayStation ) is a video game console of the 32/64-bit era, first produced by Sony Computer Entertainment in the mid-1990s. ... Instructions per second (IPS) is a measure of a computers processor speed. ... IDT was founded in 1980 as a semiconductor vendor. ... Toshiba Corporations headquarters (Center) in Hamamatsucho, Tokyo Toshiba Corporation sales by division for year ending March, 31 2005 Toshiba Corporation ) (TYO: 6502 ) is a multinational high technology electrical and electronics manufacturing firm, headquartered in Tokyo, Japan. ... System-on-a-chip (SoC or SOC) is an idea of integrating all components of a computer system into a single chip. ... A Handheld PC, or H/PC for short, is a Microsoft term for a computer built around a form factor which is smaller than any standard notebook PC or laptop. ... Windows CE (sometimes abbreviated WinCE) is a variation of Microsofts Windows operating system for minimalistic computers and embedded systems. ... The Mongoose-V 32-bit microprocessor for spacecraft on-board computer applications is a radiation-hardened and expanded 10â€“15 MHz version of the MIPS R3000 CPU. The Mongoose was developed by Synova, Inc. ...

The R4000 series, released in 1991, extended the MIPS instruction set to a full 64-bit architecture, moved the FPU onto the main die to create a single-chip system, and operated at a radically high internal clock speed (it was introduced at 100 MHz). However, in order to achieve the clock speed the caches were reduced to 8 KB each and took three cycles to access. The high operating frequencies were achieved through the technique of deep pipelining (called super-pipelining at the time). With the introduction of the R4000 a number of improved versions soon followed, including the R4400 of 1993 which included 16 KB caches, largely bug-free 64-bit operation, and a controller for another 1 MB external (level 2) cache. In computer hardware, deep pipelining refers to a case of having a long pipeline with very simple (thin) stages. ...

MIPS, now a division of SGI called MTI, designed the lower-cost R4200, and later the even lower cost R4300, which was the R4200 with a 32-bit external bus. The Nintendo 64 used a NEC VR4300 CPU that was based upon the low-cost MIPS R4300i.[2] This section needs additional references or sources to facilitate its verification. ... NEC Corporation (Jp. ...

bottom-side view of package of R4700 Orion with the exposed silicon chip, fabricated by IDT, designed by Quantum Effect Devices
topside view of package for R4700 Orion

The R8000 (1994) was the first superscalar MIPS design, able to execute two ALU and two memory operations per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB L1 data caches), a floating-point unit, three full-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's Power Challenge computer servers in the mid 1990s and later became available in the Power Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users, and the R8000 was in the marketplace for only a year and remains fairly rare. Year 1994 (MCMXCIV) was a common year starting on Saturday (link will display full 1994 Gregorian calendar). ... Simple superscalar pipeline. ...

In 1995, the R10000 was released. This processor was a single-chip design, ran at a faster clock speed than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was out-of-order execution. Even with a single memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers. Year 1995 (MCMXCV) was a common year starting on Sunday (link will display full 1995 Gregorian calendar). ...

Recent designs have all been based upon R10000 core. The R12000 used improved manufacturing to shrink the chip and operate at higher clock rates. The revised R14000 allowed higher clock rates with additional support for DDR SRAM in the off-chip cache, and a faster front side bus clocked to 200 MHz for better throughput. Later iterations are named the R16000 and the R16000A and feature increased clock speed, additional L1 cache, and smaller die manufacturing compared with before. Static random access memory (SRAM) is a type of semiconductor memory. ... Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ... In computers, the front side bus (FSB) or system bus is the physical bi-directional data bus that carries all electronic signal information between the central processing unit (CPU) and other devices within the system such as random access memory (RAM), video cards, PCI expansion cards, hard disks, the memory...

Other members of the MIPS family include the R6000, an ECL implementation of the MIPS architecture which was produced by Bipolar Integrated Technology. The R6000 microprocessor introduced the MIPS II instruction set. Its TLB and cache architecture are different from all other members of the MIPS family. The R6000 did not deliver the promised performance benefits, and although it saw some use in Control Data machines, it quickly disappeared from the mainstream market. ECL may stand for: ECL programming language, an extensible programming language developed at Harvard Ecole Centrale de Lyon, an engineering Grande Ã‰cole (university) in Lyon, France Educational Community License, an open source license issued to academic institutions for otherwise copyrighted material Effective Character Level, a concept used in D20 games... Bipolar Integrated Technology was a semiconductor company based in Beaverton, Oregon which sold products implemented with ECL technology. ... A Translation Lookaside Buffer (TLB) is a cache in a CPU that is used to improve the speed of virtual address translation. ... Control Data Corporation, or CDC, was one of the pioneering supercomputer firms. ...

MIPS microprocessor specifications
Model Frequency [MHz] Year Process [µm] Transistors [millions] Die size [mm²] IO Pins Power [W] Voltage Dcache [k] Icache [k] Scache [k]
R2000 8-16.7 1985 2.0 0.11 -- -- -- -- 32 64 none
R3000 12-40 1988 1.2 0.11 66.12 145 4 -- 64 64 none
R4000 100 1991 0.8 1.35 213 179 15 5 8 8 1024 off-chip
R4400 100-250 1992 0.6 2.3 186 179 15 5 16 16 1024 off-chip
R4600 100-133 1994 0.64 2.2 77 179 4.6 5 16 16 512 off-chip
R5000 150-200 1996 0.35 3.7 84 223 10 3.3 32 32 1024 off-chip
R8000 75-90 1994 0.5 2.6 299 591 30 3.3 16 16 2048 off-chip
R10000 150-250 1995 0.35 6.8 299 599 30 3.3 32 32 512 off-chip
R12000 270-400 1998 0.25–0.18 6.9 204 600 20 4 32 32 1024 off-chip
RM7000 250-600 1998 0.25,0.18,0.13 18 91 304 10,6,3 3.3,2.5,1.5 16 16 256 on-chip
R14000 500-600 2001 0.13 7.2 204 527 17 -- 32 32 2048 off-chip
R16000 700-800 2002 0.11 -- -- -- 20 -- 64 64 4096 off-chip

Note: These specifications are only common processor configurations. Variations exist, especially in Level 2 cache.

## Summary of R3000 instruction set

Instructions are divided into three types: R, I and J. Every instruction starts with a 6-bit opcode. In addition to the opcode, R-type instructions specify three registers, a shift amount field, and a function field; I-type instructions specify two registers and a 16-bit immediate value; J-type instructions follow the opcode with a 26-bit jump target.[3][4]

The following are the three formats used for the core instruction set:

Type -31-                                 format (bits)                                 -0-
R opcode (6) rs (5) rt (5) rd (5) shamt (5) funct (6)
I opcode (6) rs (5) rt (5) immediate (16)

### Real instructions

These are instructions that have direct hardware implementation, as opposed to pseudoinstructions which are translated into multiple real instructions before being assembled.

• CONST denotes a constant ("immediate").
• In the following, the register numbers are only examples, and any other registers can be used in their places.
• All the following instructions are native instructions.
• Opcodes and funct codes are in hexadecimal.
Category Name Instruction syntax Meaning Format/opcode/funct Notes
Arithmetic Add add \$1,\$2,\$3 \$1 = \$2 + \$3 (signed) R 0 2016 adds two registers, extends sign to width of register
Add unsigned addu \$1,\$2,\$3 \$1 = \$2 + \$3 (unsigned) R 0 2116 as above without sign extension
Subtract sub \$1,\$2,\$3 \$1 = \$2 - \$3 (signed) R 0 2216 subtracts two registers
Subtract unsigned subu \$1,\$2,\$3 \$1 = \$2 - \$3 (unsigned) R 0 as above without sign extension
Add immediate addi \$1,\$2,CONST \$1 = \$2 + CONST (signed) I 816 Used to add constants (and also to copy one register to another "addi \$1, \$2, 0"), with sign extension
Add immediate unsigned addiu \$1,\$2,CONST \$1 = \$2 + CONST (unsigned) I 916 as above without sign extension
Multiply mult \$1,\$2 LO = ((\$1 * \$2) << 32) >> 32;
HI = (\$1 * \$2) >> 32;
R 0 1816 Multiplies two registers and puts the 64-bit result in two special memory spots - LOW and HI. Alternatively, one could say the result of this operation is: (int HI,int LO) = (64-bit) \$1 * \$2 .
Divide div \$1, \$2 LO = \$1 / \$2     HI = \$1 % \$2 R Divides two registers and puts the 32-bit integer result in LO and the remainder in HI.[3]
Data Transfer Load word lw \$1,CONST(\$2) \$1 = Memory[\$2 + CONST] I 2316 loads the word stored from: MEM[\$2+CONST] and the following 3 bytes.
Load halfword lh \$1,CONST(\$2) \$1 = Memory[\$2 + CONST] (signed) I 2516 loads the halfword stored from: MEM[\$2+CONST] and the following byte. Sign is extended to width of register.
Load halfword unsigned lhu \$1,CONST(\$2) \$1 = Memory[\$2 + CONST] (unsigned) I As above without sign extension.
Load byte lb \$1,CONST(\$2) \$1 = Memory[\$2 + CONST] (signed) I loads the byte stored from: MEM[\$2+CONST].
Load byte unsigned lbu \$1,CONST(\$2) \$1 = Memory[\$2 + CONST] (unsigned) I As above without sign extension.
Store word sw \$1,CONST(\$2) Memory[\$2 + CONST] = \$1 I stores a word into: MEM[\$2+CONST] and the following 3 bytes. The order of the operands is a large source of confusion.
Store half sh \$1,CONST(\$2) Memory[\$2 + CONST] = \$1 I stores the first half of a register (a halfword) into: MEM[\$2+CONST] and the following byte.
Store byte sb \$1,CONST(\$2) Memory[\$2 + CONST] = \$1 I stores the first fourth of a register (a byte) into: MEM[\$2+CONST].
Load upper immediate lui \$1,CONST \$1 = CONST << 16 I loads a 16-bit immediate operand into the upper 16-bits of the register specified. Maximum value of constant is 216-1
Move from high mfhi \$1 \$1 = HI R Moves a value from HI to a register. Do not use a multiply or a divide instruction within two instructions of mfhi (that action is undefined because of the MIPS pipeline).
Move from low mflo \$1 \$1 = LO R 0 1216 Moves a value from LO to a register. Do not use a multiply or a divide instruction within two instructions of mflo (that action is undefined because of the MIPS pipeline).
Move from Control Register mfcZ \$1, \$2 \$1 = Coprocessor[Z].ControlRegister[\$2] R Moves a 4 byte value from Coprocessor Z Control register to a general purpose register. Sign extension.
Move to Control Register mtcZ \$1, \$2 Coprocessor[Z].ControlRegister[\$2] = \$1 R Moves a 4 byte value from a general purpose register to a Coprocessor Z Control register. Sign extension.
Load word coprocessor lwcZ \$1,CONST(\$2) Coprocessor[Z].DataRegister[\$1] = Memory[\$2 + CONST] I Loads the 4 byte word stored from: MEM[\$2+CONST] into a Coprocessor data register. Sign extension.
Store word coprocessor swcZ \$1,CONST(\$2) Memory[\$2 + CONST] = Coprocessor[Z].DataRegister[\$1] I Stores the 4 byte word held by a Coprocessor data register into: MEM[\$2+CONST]. Sign extension.
Logical And and \$1,\$2,\$3 \$1 = \$2 & \$3 R Bitwise and
And immediate andi \$1,\$2,CONST \$1 = \$2 & CONST I
Or or \$1,\$2,\$3 \$1 = \$2 | \$3 R Bitwise or
Or immediate ori \$1,\$2,CONST \$1 = \$2 | CONST I
Exclusive or xor \$1,\$2,\$3 \$1 = \$2 ^ \$3 R
Nor nor \$1,\$2,\$3 \$1 = ~(\$2 | \$3) R Bitwise nor
Set on less than slt \$1,\$2,\$3 \$1 = (\$2 < \$3) R Tests if one register is less than another.
Set on less than immediate slti \$1,\$2,CONST \$1 = (\$2 < CONST) I Tests if one register is less than a constant.
Bitwise Shift Shift left logical sll \$1,\$2,CONST \$1 = \$2 << CONST R shifts CONST number of bits to the left (multiplies by 2CONST)
Shift right logical srl \$1,\$2,CONST \$1 = \$2 >> CONST R shifts CONST number of bits to the right - zeros are shifted in (divides by 2CONST). Note that this instruction only works as division of a two's complement number if the value is positive.
Shift right arithmetic sra \$1,\$2,CONST $1 = 2 >> CONST +$
$bigg(bigg(sum_{n=1}^{CONST}2^{31-n}bigg)cdot 2 >> 31 bigg)$
R shifts CONST number of bits - the sign bit is shifted in (divides 2's complement number by 2CONST)
Conditional branch Branch on equal beq \$1,\$2,CONST if (\$1 == \$2) go to PC+4+CONST I Goes to the instruction at the specified address if two registers are equal.
Branch on not equal bne \$1,\$2,CONST if (\$1 != \$2) go to PC+4+CONST I Goes to the instruction at the specified address if two registers are not equal.
Unconditional jump Jump j CONST goto address CONST J Unconditionally jumps to the instruction at the specified address.
Jump register jr \$1 goto address \$1 R Jumps to the address contained in the specified register
Jump and link jal CONST \$31 = PC + 4; goto CONST J For procedure call - used to call a subroutine, \$31 holds the return address; returning from a subroutine is done by: jr \$31

NOTE: in the branching and jump instructions, the offset can be replaced by a label present somewhere in the code. In computer programming, a bitwise operation operates on one or two bit patterns or binary numerals at the level of their individual bits. ... In computer programming, a bitwise operation operates on one or two bit patterns or binary numerals at the level of their individual bits. ... In computer programming, a bitwise operation operates on one or two bit patterns or binary numerals at the level of their individual bits. ... Twos complement is the most popular method of signifying negative integers in computer science. ...

NOTE: that there is no corresponding "load lower immediate" instruction; this can be done by using addi (add immediate, see below) or ori (or immediate) with the register \$0 (whose value is always zero). For example, both `addi \$1, \$0, 100` and `ori \$1, \$0, 100` load the decimal value 100 into register \$1.

NOTE: An arithmetic operation with signed immediates differs from one with unsigned ones in that it does not throw an exception. Subtracting an immediate can be done with adding the negation of that value as the immediate.

### Pseudo instructions

These instructions are accepted by the MIPS assembler, however they are not real instructions within the MIPS instruction set. Instead, the assembler translates them into sequences of real instructions.

Name instruction syntax Real instruction translation meaning
Load Immediate li \$1, IMMED[31:0] lui \$1, IMMED[31:16]; ori \$1,\$1, IMMED[15:0] \$1 = 32 bit Immediate value
Branch greater than bgt if(R[rs]>R[rt]) PC=Label
Branch less than blt if(R[rs]<R[rt]) PC=Label
Branch greater than or equal bge if(R[rs]>=R[rt]) PC=Label
branch less than or equal ble if(R[rs]<=R[rt]) PC=Label
branch greater than unsigned bgtu if(R[rs]=>R[rt]) PC=Label
branch greater than zero bgtz if(R[rs]>0) PC=Label

### Some other important instructions

• nop (no operation) (machine code 0x00000000, interpreted by CPU as sll \$0,\$0,0)
• break (breaks the program, used by debuggers)
• syscall (used for system calls to the operating system)
• a full set of Floating point instructions for both single precision and double precision operands

## Compiler Register Usage

The hardware architecture specifies that:

• General purpose register \$0 always returns a value of 0 .
• General purpose register \$31 is used as the link register for jump and link instructions.
• HI and LO are used to access the multiplier/divider results.

These are the only hardware restrictions on the usage of the general purpose registers.

The various MIPS tool-chains implement specific calling conventions that further restrict how the registers are used. These conventions are totally maintained by the tool-chain software and are not required by the hardware.

Registers
Name Number Use Callee must preserve?
\$zero \$0 constant 0 N/A
\$at \$1 assembler temporary no
\$v0–\$v1 \$2–\$3 Values for function returns and expression evaluation no
\$a0–\$a3 \$4–\$7 function arguments no
\$t0–\$t7 \$8–\$15 temporaries no
\$s0–\$s7 \$16–\$23 saved temporaries yes
\$t8–\$t9 \$24–\$25 temporaries no
\$k0–\$k1 \$26–\$27 reserved for OS kernel no
\$gp \$28 global pointer yes
\$sp \$29 stack pointer yes
\$fp \$30 frame pointer yes

Registers that are preserved across a call are registers that (by convention) will not be changed by a system call or procedure (function) call. For example, \$s-registers must be saved to the stack by a procedure that needs to use them, and \$sp and \$fp are always incremented by constants, and decremented back after the procedure is done with them (and the memory they point to). By contrast, \$ra is changed automatically by any normal function call (ones that use jal), and \$t-registers must be saved by the program before any procedure call (if the program needs the values inside them after the call). To meet Wikipedias quality standards, this article or section may require cleanup. ... A framepointer or frame pointer is a pointer to the current stack frame. ... In both conventional and electronic messaging, a return address is an explicit inclusion of the address of the person sending the message. ...

## Simulators

There is a freely available "MIPS32 Simulator" (earlier versions simulated only the R2000/R3000) called SPIM for several operating systems (specifically Unix or GNU/Linux; Mac OS X; MS Windows 95, 98, NT, 2000, XP; and DOS) which is good for learning MIPS assembly language programming and the general concepts of RISC-assembly language programming: http://www.cs.wisc.edu/~larus/spim.html SPIM is a simulated assembly language written for MIPS architecture R2000 and R3000 processors, copyrighted by James R. Larus. ...

EduMIPS64 is a GPL graphical cross-platform MIPS64 CPU simulator, written in Java/Swing. It supports a wide subset of the MIPS64 ISA and allows the user to graphically see what happens in the pipeline when an assembly program is run by the CPU. It has educational purposes and is used in some Computer Architecture courses in Universities around the world. More info at http://www.edumips.org

MARS is another GUI based MIPS emulator designed for use in education, specifically for use with Hennessy's Computer Organization and Design. More information is available at http://courses.missouristate.edu/KenVollmar/MARS/

More advanced free MIPS emulators are available from the GXemul (formerly known as the mips64emul project) and QEMU projects, which emulate not only the various MIPS III and higher microprocessors (from the R4000 through the R10000), but also entire computer systems which use the microprocessors. For example, GXemul can emulate both a DECstation with a MIPS R4400 CPU (and boot to Ultrix), and an SGI O2 with a MIPS R10000 CPU (although the ability to boot Irix is limited), among others, as well as the various framebuffers, SCSI controllers, and the like which comprise those systems. GXemul (formerly known as mips64emul) is a computer architecture emulator originally written to emulate computer systems using the MIPS instruction set, and is available as free software under a revised BSD-style license. ... It has been suggested that Qemu-Launcher be merged into this article or section. ... A DECstation 5000/120 The DECstation was a brand of computers built by DEC, and refers to two distinct lines of computer systemsâ€”the first released in the 1970s as a word processing system, and the second (and more widely known) released in 1989 as computer workstations based on the... Ultrix (officially all-caps ULTRIX) was the brand name of Digital Equipment Corporations (DEC) native Unix systems. ... An SGI O2 (1996) SGI O2 Workstation The O2 is an entry-level Unix workstation introduced in 1996 by Silicon Graphics (SGI) to replace their earlier Indy series. ... IRIX is a computer operating system developed by Silicon Graphics, Inc. ... The framebuffer is a part of RAM in a computer allocated to hold the graphics information for one frame or picture. ... This article or section does not cite any references or sources. ...

Commercial simulators are available especially for the embedded use of MIPS processors, for example Virtutech Simics (MIPS 4Kc and 5Kc, PMC RM9000, QED RM7000), VaST Systems (R3000, R4000), and CoWare (the MIPS4KE, MIPS24K, MIPS25Kf and MIPS34K). Simics is a full-system simulator from Virtutech capable of running unchanged production binaries of the target hardware at high-performance speeds. ... CoWare, Inc is the leading supplier of platform-driven electronic system level (ESL) design software and services. ...

Examples of system calls (used by SPIM)
service Trap code Input Output Notes
print_int \$v0 = 1 \$a0 = integer to print prints \$a0 to standard output
print_float \$v0 = 2 \$f12 = float to print prints \$f12 to standard output
print_double \$v0 = 3 \$f12 = double to print prints \$f12 to standard output
print_string \$v0 = 4 \$a0 = address of first character prints a character string to standard output
read_int \$v0 = 5 integer read from standard input placed in \$v0
read_float \$v0 = 6 float read from standard input placed in \$f0
read_double \$v0 = 7 double read from standard input placed in \$f0
sbrk \$v0 = 9 \$a0 = number of bytes required \$v0= address of allocated memory Allocates memory from the heap
exit \$v0 = 10
print_char \$v0 = 11 \$a0 = character (low 8 bits)
read_char \$v0 = 12 \$v0 = character (no line feed) echoed
file_open \$v0 = 13 \$a0 = full path (zero terminated string with no line feed), \$a1 = flags, \$a2 = permission (read = 0x100, write = 0x80) \$v0 = file descriptor
file_read \$v0 = 14 \$a0 = file descriptor, \$a1 = buffer address, \$a2 = amount to read in bytes \$v0 = amount of data in buffer from file (-1 = error, 0 = end of file)
file_write \$v0 = 15 \$a0 = file descriptor, \$a1 = buffer address, \$a2 = amount to write in bytes \$v0 = amount of data in buffer to file (-1 = error, 0 = end of file)
file_close \$v0 = 16 \$a0 = file descriptor

Flags:

OR Create = 0x100, Truncate = 0x200, Append = 0x8

OR Text = 0x4000, Binary = 0x8000

## Notes

1. ^ SGI announcing the end of MIPS
2. ^ NEC Offers Two High Cost Performance 64-bit RISC Microprocessors
3. ^ a b MIPS R3000 Instruction Set Summary
4. ^ MIPS Instruction Reference

• Patterson and Hennessy: Computer Organization and Design. The Hardware/Software Interface. Morgan Kaufmann Publishers. ISBN 1-55860-604-1
• Dominic Sweetman: See MIPS Run. Morgan Kaufmann Publishers. ISBN 1-55860-410-3
• Erin Farquhar & Philip Bunce: MIPS Programmer's Handbook. Morgan Kaufmann Publishers. ISBN 1-55860-297-6

• DLX, a very similar architecture designed by John L. Hennessy (creator of MIPS) for teaching purposes
• Loongson, a MIPS-like processor architecture developed at Chinese Academy of Sciences
• MIPS-X, developed as a follow-on project to the MIPS architecture

The DLX is a RISC processor architecture by John L. Hennessy and David A. Patterson, the principal designers of the MIPS and the Berkeley RISC designs (respectively), the two benchmark examples of RISC design. ... John LeRoy Hennessy, the founder of MIPS Computer Systems Inc. ... This article or section needs copy editing for grammar, style, cohesion, tone and/or spelling. ... MIPS-X is a microprocessor and instruction set architecture developed as a follow-on project to the MIPS architecture at Stanford University by the same team that developed MIPS. The project started in 1984, and its final form was described in a set of papers released in 1986-1987. ...

Results from FactBites:

 About Us - MIPS Technologies -MIPS Everywhere - MIPS Technologies (686 words) At the heart of MIPS technology is the MIPS architecture, developed 20 years ago by Stanford University engineering professor John Hennessy, now president of Stanford. Today, the MIPS architecture is an industry standard and the performance leader within the embedded industry. MIPS Technologies is a leading provider of industry-standard processor architectures and cores for digital consumer, networking, personal entertainment, communications and business applications.
 NationMaster - Encyclopedia: MIP (560 words) A maximum intensity projection (MIP) is a computer visualization method for 3D data that projects in the visualization plane the voxels with maximum intensity that fall in the way of parallel rays traced from the viewpoint to the plane of projection. By the late 1990s MIPS was a powerhouse in the embedded processor field, and in 1997 the 48-millionth MIPS-based CPU shipped, making it the first RISC CPU to outship the famous Motorola 68000 family. A more feature-rich MIPS emulator is available from the GXemul project (formerly known as the mips64emul project), which emulates not only the various MIPS III and higher microprocessors (from the R4000 through the R10000), but also emulates entire computer systems which use the microprocessors.
More results at FactBites »

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