FACTOID # 13: New York has America's lowest percentage of residents who are veterans.
 
 Home   Encyclopedia   Statistics   States A-Z   Flags   Maps   FAQ   About 
   
 
WHAT'S NEW
 

SEARCH ALL

FACTS & STATISTICS    Advanced view

Search encyclopedia, statistics and forums:

 

 

(* = Graphable)

 

 


Encyclopedia > INMOS transputer
T414B transputer chip
T414B transputer chip

The INMOS transputer (the all-lowercase "transputer" was the official written form) was a pioneering concurrent computing microprocessor design of the 1980s from INMOS, a British semiconductor company based in Bristol (the University of the West of England in Bristol had, for a while, a transputer centre). For some time in the late 1980s many considered the transputer to be the next great design for the future of computing. Image File history File linksMetadata IMST414B-G20S.JPG‎ INMOS IMS T414B-G20S transputer chip. ... Image File history File linksMetadata IMST414B-G20S.JPG‎ INMOS IMS T414B-G20S transputer chip. ... Concurrent computing is the concurrent (simultaneous) execution of multiple interacting computational tasks. ... A microprocessor (sometimes abbreviated µP) is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... The 1980s refers to the years of 1980 to 1989. ... The INMOS Transputer was a pioneering parallel computing microprocessor design of the 1980s from INMOS, a small English company. ... Semiconductor devices are electronic components that exploit the electronic properties of semiconductor materials, principally silicon, germanium, and gallium arsenide. ... Bristol (IPA: ) is a city, unitary authority and ceremonial county in South West England, 115 miles (185 km) west of London and between the cities of Bath, Gloucester and the borough of Swindon. ...


Today, this interesting chip is largely forgotten. Whilst ultimately a commercial failure, the transputer architecture was highly influential in provoking new ideas in computer architecture, several of which have re-emerged in different forms in modern systems.

Contents

Background

In the early 1980s, it appeared that conventional CPUs were reaching their performance limits. Up to that time, the amount of circuitry designers could place on a chip was limited primarily by manufacturing issues. But with continued improvements in the"fabbing" process (fabricating), this restriction vanished and soon the problem became that the chips could hold more circuitry than the designers knew how to use. Soon the traditional CISC designs were reaching a performance plateau, and it wasn't clear it could be overcome. Die of an Intel 80486DX2 microprocessor (actual size: 12×6. ... A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ...


It seemed that the only way forward was to increase the use of parallelism, the use of several CPUs that would work together to solve several tasks at the same time. This depended on the machines in question being able to run several tasks at once, a process known as multitasking. This had generally been too difficult for previous CPU designs to handle, but more recent designs were able to accomplish it effectively. It was clear that in the future this would be a feature of all operating systems. In computing, multitasking is a method by which multiple tasks, also known as processes, share common processing resources such as a CPU. In the case of a computer with a single CPU, only one task is said to be running at any point in time, meaning that the CPU is... An operating system (OS) is a computer program that manages the hardware and software resources of a computer. ...


A side effect of most multitasking design is that it often also allows the processes to be run on physically different CPUs, in which case it is known as multiprocessing. A low-cost CPU built with multiprocessing in mind could allow the speed of a machine to be increased by adding additional CPUs, potentially far more cheaply than by using a single faster CPU design. Multiprocessing is traditionally known as the use of multiple concurrent processes in a system as opposed to a single process at any one instant. ...


Design

The transputer (transistor computer) was the first general purpose microprocessor designed specifically to be used in parallel computing systems. The goal was to produce a family of chips ranging in power and cost that could be wired together to form a complete computer. The name was selected to indicate the role the individual transputers would play: numbers of them would be used as basic building blocks, just as transistors had earlier.


Originally the plan was to make the transputer cost only a few dollars per unit. INMOS saw them being used for practically everything, from operating as the main CPU for a computer to acting as a channel controller for disk drives in the same machine. Spare cycles on any of these transputers could be used for other tasks, greatly increasing the overall performance of the machines. A channel controller is a simple CPU used to handle the task of moving data to and from the memory of a computer. ...


Even a single transputer would have all the circuitry needed to work by itself, a feature more commonly associated with microcontrollers. The intention was to allow transputers to be connected together as easily as possible, without the requirement for a complex bus (or motherboard). Power and a simple clock signal had to be supplied, but little else: RAM, a RAM controller, bus support and even an RTOS were all built in. The integrated circuit from an Intel 8742, an 8-bit microcontroller that includes a CPU running at 12 MHz, 128 bytes of RAM, 2048 bytes of EPROM, and I/O in the same chip. ... Random access memory (usually known by its acronym, RAM) is a type of data store used in computers. ... A Real Time Operating System or RTOS is an operating system that has been developed for real-time applications. ...


Links

The basic design of the transputer included serial links that allowed it to communicate with up to four other transputers, each at 5, 10 or 20 Mbit/s – which was very fast for the 1980s. Any number of transputers could be connected together over even longish links (tens of metres) to form a single computing "farm". A hypothetical desktop machine might have two of the "low end" transputers handling I/O tasks on some of their serial lines (hooked up to appropriate hardware) while they talked to one of their larger cousins acting as a CPU on another. In computing, input/output, or I/O, is the collection of interfaces that different functional units (sub-systems) of an information processing system use to communicate with each other, or the signals (information) sent through those interfaces. ... Die of an Intel 80486DX2 microprocessor (actual size: 12×6. ...


There were limits to the size of a system that could be built in this fashion. Since each transputer was linked to another in a fixed point-to-point layout, sending messages to a more distant transputer required the messages to be relayed each chip on the line. This introduced a delay with every "hop" over a link, leading to long delays on large nets. To solve this problem INMOS also provided a zero-delay switch that connected up to 32 transputers (or switches) into even larger networks.


Booting

Transputers could be booted over the network links (as opposed to the memory as in most machines) so a single transputer could start up the entire network. There was a pin called BootFromROM that when asserted caused the transputer to start two bytes from the top of memory (sufficient for up to a 256 byte backward jump, usually out of ROM). When this pin was not asserted, the first byte that arrived down any link was the length of a bootstrap to be downloaded, which was placed in low memory and run. The 'special' lengths of 0 and 1 were reserved for 'peek' and 'poke' - allowing inspection and changing of RAM in an unbooted transputer. After a peek (which required an address) or a poke (which took a word address, and a word of data - 16 or 32 bit depending on the basic word width of the transputer variant) the transputer would return to waiting for a bootstrap.


Scheduler

Supporting the links was additional circuitry that handled scheduling of the traffic over them. Processes waiting on communications would automatically pause while the networking circuitry finished its reads or writes. Other processes running on the transputer would then be given that processing time. It included two priority levels to improve real-time and multiprocessor operation. The same logical system was used to communicate between programs running on a single transputer, implemented as "virtual network links" in memory. So programs asking for any input or output automatically paused while the operation completed, a task that normally required the operating system to handle as the arbiter of hardware. Operating systems on the transputer did not have to handle scheduling: in fact, one could consider the chip itself to have an OS inside it. Priority level: In the Telecommunications Service Priority system, the level that may be assigned to an NS/EP telecommunications service, which level specifies the order in which provisioning or restoration of the service is to occur relative to other NS/EP or non-NS/EP telecommunication services. ... Wikipedia does not have an article with this exact name. ... Multiprocessing is traditionally known as the use of multiple concurrent processes in a system as opposed to a single process at any one instant. ...


To include all this functionality on a single chip, the transputer's core logic was simpler than most CPUs. While some have called it a RISC due to its rather spare nature (and because that was a desirable marketing buzzword at the time), it was heavily microcoded, had a limited register set, and complex memory-to-memory instructions, all of which place it firmly in the CISC camp. Unlike register-heavy load-store RISC CPUs, the transputer had only three data registers, which behaved as a stack. In addition a Workspace Pointer pointed to a conventional memory stack, easily accessible via the Load Local and Store Local instructions. This allowed for very fast context switching by simply changing the workspace pointer to the memory used by another process (a technique used in a number of contemporary designs). The three register stack contents were not preserved past certain instructions, like Jump, when the transputer could do a context switch. Reduced Instruction Set Computer (RISC), is a microprocessor CPU design philosophy that favors a smaller and simpler set of instructions that all take about the same amount of time to execute. ... A buzzword (also known as a fashion word or vogue word) is an idiom, often a neologism, commonly used in managerial, technical, administrative, and sometimes political environments. ... A microprogram is a program consisting of microcode that controls the different parts of a computers central processing unit (CPU). ... A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... A context switch is the computing process of storing and restoring the state (context) of a CPU such that multiple processes can share a single CPU resource. ...


Instruction set

The transputer instruction set comprised 8-bit instructions divided into opcode and operand nibbles. The "upper" nibble contained the 16 possible primary instruction codes, making it one of the very few commercialized minimal instruction set computers. The "lower" nibble contained the single immediate constant operand, commonly used as an offset relative to the Workspace (memory stack) pointer. Two prefix instructions allowed construction of larger constants by prepending their lower nibbles to the operands of following instructions. Additional instructions were supported via the Operate (Opr) instruction code, which decoded the constant operand as an extended zero-operand opcode, providing for almost endless and easy instruction set expansion as newer implementations of the transputer were introduced. Microprocessors perform operations using binary bits (on/off/1or0). ... In mathematics, an operand is one of the inputs (arguments) of an operator. ... A nibble (or less commonly, nybble) is the computing term for the aggregation of four bits, or half an octet (an octet being an 8-bit byte). ... MISC (Minimal Instruction Set Computer) is a processor architecture with a very small number of basic operations and corresponding opcodes. ... Look up prefix in Wiktionary, the free dictionary. ...


The 16 'primary' one-operand instructions were :-

Mnemonic Description
J Jump — add immediate operand to instruction pointer.
LDLP Load Local Pointer — load a Workspace-relative pointer onto the top of the register stack
PFIX Prefix — general way to increase lower nibble of following primary instruction
LDNL Load non-local — load a value offset from address at top of stack
LDC Load constant — load constant operand onto the top of the register stack
LDNLP Load Non-local pointer — Load address, offset from top of stack
NFIX Negative prefix — general way to negate (and possibly increase) lower nibble
LDL Load Local — load value offset from Workspace
ADC Add Constant — add constant operand to top of register stack
CALL Subroutine call — push instruction pointer and jump
CJ Conditional jump — depending on value at top of register stack
AJW Adjust workspace — add operand to workspace pointer
EQC Equals constant — test if top of register stack equals constant operand
STL Store local - store at constant offset from workspace
STNL Store non-local - store at address offset from top of stack
OPR Operate - general way to extend instruction set

All these instructions take a constant, representing an offset or an arithmetic constant. If this constant was less than 16, all these instructions coded to a single byte.


The first 16 'secondary' zero-operand instructions (using the OPR primary instruction) were :-

Mnemonic Description
REV Reverse — swap two top items of register stack
LB Load byte
BSUB Byte subscript
ENDP End process
DIFF Difference
ADD Add
GCALL General Call - swap top of stack and instruction pointer
IN Input — receive message
PROD Product
GT Greater Than — the only comparison instruction
WSUB Word subscript
OUT Output — send message
SUB Subtract
STARTP Start Process
OUTBYTE Output Byte — send single-byte message
OUTWORD Output word — send single-word message

TRAMs

To provide an easy means of prototyping, constructing and configuring multiple-transputer systems, INMOS introduced the TRAM (TRAnsputer Module) standard in 1987. A TRAM was essentially a building block daughterboard comprising a transputer and, optionally, external memory and/or peripheral devices, with simple standardised connectors providing power, transputer links, clock and system signals. Various sizes of TRAM were defined, from the basic Size 1 TRAM (3.66 in by 1.05 in) up to Size 8 (3.66 in by 8.75 in). INMOS produced a range of TRAM motherboards for various host buses such as ISA, MicroChannel or VMEbus. A daughterboard or daughtercard is a circuit board meant to be an extension or daughter of a motherboard (or mainboard), or occasionally another card. ... Sony Playstation motherboard A motherboard, also known as main board, logic board or system board, is the central or primary circuit board making up a complex electronic system, such as a computer. ... Industry Standard Architecture (in practice almost always shortened to ISA) is a computer bus standard for IBM compatible computers. ... Micro Channel architecture (in practice almost always shortened to MCA) was a proprietary 16 or 32-bit parallel computer bus created by IBM in the 1980s for use on their new PS/2 computers. ... VMEbus is a computer bus standard originally developed for the Motorola 68000 line of CPUs, but later widely used for many applications and standardized by the IEC as ANSI/IEEE 1014-1987. ...


Software

Transputers were intended to be programmed using the occam programming language, based on the CSP process calculus. In fact it is fair to say that the transputer was built specifically to run occam, even more so than contemporary CISC designs were built to run languages like Pascal or C. Occam supported concurrency and channel-based inter-process or inter-processor communication as a fundamental part of the language. With the parallelism and communications built into the chip and the language interacting with it directly, writing code for things like device controllers became a triviality – even the most basic code could watch the serial ports for I/O, and would automatically sleep when there was no data. Occam is a parallel programming language that builds on Communicating Sequential Processes (CSP) and shares many of their features. ... In computer science, Communicating Sequential Processes (CSP) is a formal language for describing patterns of interaction in concurrent systems. ... In the first half of the 20th century, various formalisms were proposed to capture the informal concept of computable function, μ-recursive functions, Turing Machines and the lambda calculus possibly being the most well-known examples today. ... A Complex Instruction Set Computer (CISC) is an instruction set architecture (ISA) in which each instruction can indicate several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... Pascal is an imperative computer programming language, developed in 1970 by Niklaus Wirth as a language particularly suitable for structured programming. ... C is a general-purpose, procedural, imperative computer programming language developed in 1972 by Dennis Ritchie at the Bell Telephone Laboratories for use with the Unix operating system. ... Wikiquote has a collection of quotations related to: Edsger Dijkstra The Dining Philosophers, a classic problem involving concurrency and shared resources In computer science, concurrency is a property of systems which consist of computations that execute overlapped in time, and which may permit the sharing of common resources between those...


The initial occam development environment for the transputer was the INMOS D700 Transputer Development System (TDS). This was an unorthodox integrated development environment incorporating an editor, compiler, linker and (post-mortem) debugger. The TDS was itself a transputer application written in occam. The TDS text editor was notable in that it was a folding editor, allowing blocks of code to be hidden and revealed, to make the structure of the code more apparent. Unfortunately, the combination of an unfamiliar programming language and equally unfamiliar development environment did nothing for the early popularity of the transputer. Later, INMOS would release more conventional occam cross-compilers, the occam 2 Toolsets. An example of text folding within Vim. ...


Implementations of more mainstream programming languages, such as C, FORTRAN, Ada and Pascal were also later released by both INMOS and third-party vendors. These usually included language extensions or libraries providing, in a less elegant way, occam-like concurrency and channel-based communication. Fortran (previously FORTRAN[1]) is a general-purpose[2], procedural,[3] imperative programming language that is especially suited to numeric computation and scientific computing. ... Ada is a structured, statically typed imperative computer programming language designed by a team led by Jean Ichbiah of CII Honeywell Bull under contract by the US Navy during 1977–1983. ...


The transputer's lack of support for virtual memory inhibited the porting of mainstream variants of the UNIX operating system, though ports of UNIX-like operating systems (such as Minix and Idris from Whitesmiths) were produced. An advanced UNIX-like distributed operating system, HeliOS, was also designed specifically for multi-transputer systems by Perihelion Software. Filiation of Unix and Unix-like systems Unix (officially trademarked as UNIX®) is a computer operating system originally developed in the 1960s and 1970s by a group of AT&T employees at Bell Labs including Ken Thompson, Dennis Ritchie and Douglas McIlroy. ... Diagram of the relationships between several Unix-like systems A Unix-like operating system is one that behaves in a manner similar to a Unix system, while not necessarily conforming to or being certified to any version of the Single UNIX Specification. ... MINIX is an open source, Unix-like operating system (OS) based on a microkernel architecture. ... Idris is an operating system released by Whitesmiths, of Westford, Massachusetts. ... Whitesmiths was the first commercial C programming language compiler. ... This article or section should include material from Distributed programming This article or section should include material from Distributed system Distributed computing is the process of aggregating the power of several computing entities to collaboratively run a single computational task in a transparent and coherent way, so that they appear... Helios in his chariot In Greek mythology the sun was personified as Helios or Helius (Greek Ἥλιος / ἥλιος). Homer often calls him Titan and Hyperion. ... Perihelion Software was a United Kingdom company founded in 1986 by Dr. Tim King along with a number of colleagues who had all worked together at MetaComCo on AmigaOS and written compilers for both the Amiga and the Atari ST. Perihelion produced an operating system for the INMOS Transputer called...


Implementations

The first transputers were announced in 1983 and released in 1984. 1983 (MCMLXXXIII) was a common year starting on Saturday of the Gregorian calendar. ... 1984 (MCMLXXXIV) was a leap year starting on Sunday of the Gregorian calendar. ...


In keeping with their role as microcontroller-like devices, they included on-board RAM and a built-in RAM controller which enabled more memory to be added without any additional hardware. Unlike other designs, transputers did not include I/O lines: these were to be added with hardware attached to the existing serial links. There was one 'Event' line, similar to a conventional processor's interrupt line. Treated as a channel, a program could 'input' from the event channel, and proceed only after the event line was asserted. The integrated circuit from an Intel 8742, an 8-bit microcontroller that includes a CPU running at 12 MHz, 128 bytes of RAM, 2048 bytes of EPROM, and I/O in the same chip. ... Look up RAM, Ram, ram in Wiktionary, the free dictionary. ...


All transputers ran from an external 5 MHz clock input; this was multiplied to provide the processor clock.


The transputer did not include an MMU or a virtual memory system. MMU, short for memory management unit, is a class of computer hardware components responsible for handling memory accesses requested by the CPU. Among the functions of such devices are the translation of virtual addresses to physical addresses (i. ... It has been suggested that this article be split into multiple articles. ...


Transputer variants (excepting the cancelled T9000) can be categorised into three groups: the 16-bit T2 series, the 32-bit T4 series and the 32-bit T8 series with 64-bit IEEE 754 floating-point support. In computer science, 16-bit is an adjective used to describe integers that are at most two bytes wide, or to describe CPU architectures based on registers, address buses, or data buses of that size. ... 32-bit is a term applied to processors, and computer architectures which manipulate the address and data in 32-bit chunks. ... The IEEE Standard for Binary Floating-Point Arithmetic (IEEE 754) is the most widely-used standard for floating-point computation, and is followed by many CPU and FPU implementations. ... This article or section is in need of attention from an expert on the subject. ...


16-bit

The prototype 16-bit transputer was the S43, which lacked the scheduler and DMA-controlled block transfer on the links. At launch, the T212 and M212 (the latter with an on-board disk controller) were the 16-bit offerings. The T212 was available in 17.5 and 20 MHz processor clock speed ratings. The T212 was superseded by the T222, with on-chip RAM expanded from 2 kB to 4kB, and, later, the T225. This added debugging breakpoint support (by extending the instruction J 0) plus some extra instructions from the T800 instruction set. Both the T222 and T225 ran at 20 MHz. A breakpoint, in software development, is an intentional stopping or pausing place in a program, put in place for debugging purposes. ...


32-bit

At launch, the T414 was the 32-bit offering. Originally, the first 32-bit variant was to be the T424, but fabrication difficulties meant that this was redesigned as the T414 with 2 kB on-board RAM instead of the intended 4 kB. The T414 was available in 15 and 20 MHz varieties. The RAM was later reinstated to 4 kB on the T425 (in 20, 25 and 30 MHz varieties), which also added the J 0 breakpoint support and extra T800 instructions. The T400, released in September 1989, was a low-cost 20 MHz T425 derivative with 2 kB and two instead of four links, intended for the embedded systems market. 1989 (MCMLXXXIX) was a common year starting on Sunday of the Gregorian calendar. ... What is an Embedded System? Electronic devices that incorporate a computer(usually a microprocessor) within their implementation. ...


Floating point

The second-generation T800 transputer, introduced in 1987, included a 64-bit floating point unit and three additional registers for floating point use, in addition to an extended instruction set. It also had 4 kB of on-board RAM and was available in 20 or 25 MHz versions. Breakpoint support was added in the later T801 and T805, the former featuring separate address and data buses to improve performance. The T805 was also later available as a 30 MHz part. 1987 (MCMLXXXVII) was a common year starting on Thursday of the Gregorian calendar. ...


An enhanced T810 was planned, which would have had more RAM, more and faster links, extra instructions and improved microcode, but this was cancelled around 1990. 1990 (MCMXC) was a common year starting on Monday of the Gregorian calendar. ...


INMOS also produced a variety of support chips for the transputer processors, such as the C004 32-way link switch and the C012 "link adapter" which allowed transputer links to be interfaced to an 8-bit data bus.


Markets

While the transputer was simple but powerful compared to many contemporary designs, it never came close to meeting its goal of being used universally in both CPU and microcontroller roles. In the microcontroller realm, the market was dominated by 8-bit machines where cost was the only serious consideration. Here, even the T2s were too powerful and expensive for most users.


In the computer desktop/workstation world, the transputer was fairly fast (operating at about 10 MIPS at 20 MHz). This was excellent performance for the early 1980s, but by the time the FPU-equipped T800 was shipping, other RISC designs had surpassed it. This could have been mitigated to a large extent if machines had used multiple transputers as planned, but T800s cost about $400 each when introduced, which meant a poor price/performance ratio. Few transputer-based workstation systems were designed; the most notable probably being the Atari Transputer Workstation. It has been suggested that Desktop metaphor,Paper paradigm be merged into this article or section. ... Sun SPARCstation 1+, 25mhz RISC processor from early 1990s A workstation, such as a Unix workstation, RISC workstation or engineering workstation, is a high-end desktop or deskside microcomputer designed for technical applications. ... Million instructions per second (MIPS) is a measure of a computers processor speed. ... The Atari Transputer Workstation (also known as ATW-800, or simply ATW) was a workstation class computer released by Atari in the late 1980s. ...


The transputer was more successful in the field of massively parallel computing, where several vendors produced transputer-based systems in the late 1980s. These included Meiko (founded by ex-INMOS employees), Floating Point Systems, Parsytec and Parsys. Massively parallel is a description which appears in computer science, life science, medical diagnositcs, and other fields. ... The 1980s refers to the years of 1980 to 1989. ... Meiko Scientific was a supercomputer company founded by members of the design team working on the INMOS Transputer. ... Floating Point Systems Inc. ...


T9000

INMOS improved on the performance of the T8 series transputers with the introduction of the T9000 (code-named H1 during development). The T9000 shared most features with the T800, but moved several pieces of the design into hardware and added several features for superscalar support. Unlike the earlier models, the T9000 had a true 16 kB high-speed cache instead of RAM, but also allowed it to be used as memory and included MMU-like functionality to handle all of this (known as the PMI). For additional speed the T9000 cached the top 32 locations on the stack, instead of three as in earlier versions. Simple superscalar pipeline. ... Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ...


The T9000 used a five stage pipeline for even more speed. An interesting addition was the grouper which would collect instructions out of the cache and group them into larger packages of 4 bytes to feed the pipeline faster. Groups then completed in a single cycle, as if they were single larger instructions working on a faster CPU.


The link system was upgraded to a new 100 MHz mode, but unlike the previous systems the links were no longer downwardly compatible. This new packet-based link protocol was called DS-Link and later formed the basis of the IEEE 1355 serial interconnect standard. The T9000 also added link routing hardware called the VCP (Virtual Channel Processor) which changed the links from point-to-point to a true network, allowing for the creation of any number of virtual channels on the links. This meant programs no longer had to be aware of the physical layout of the connections. A range of DS-Link support chips were also developed, including the C104 32-way crossbar switch, and the C101 link adapter. IEEE-1355, IEC 14575, or ISC 14575 is a data communications standard, the IEEE Standard for Heterogeneous Interconnect (HIC). ...


Long delays in the T9000's development meant that the faster load-store designs were already outperforming it by the time it was to be released. In fact it consistently failed to reach its own performance goal of beating by a factor of ten the T800: when the project was finally cancelled it was still achieving only about 36 MIPS at 50 MHz. The production delays gave rise to the quip that the best host architecture for a T9000 was an overhead projector.


This was too much for INMOS, who didn't have the funding needed to continue development. By this time, the company had been sold to SGS-Thomson (now STMicroelectronics), whose focus was the embedded systems market, and eventually the T9000 project was abandoned. However, a comprehensively redesigned 32-bit transputer intended for embedded applications, the ST20 series, was later produced, utilising some technology developed for the T9000. The ST20 core was incorporated into chipsets for set-top box and GPS applications. STMicroelectronics is an international leading supplier of semiconductors. ... The term set-top box (STB) describes a device that connects to a television and some external source of signal, and turns the signal into content then displayed on the screen. ... Over fifty GPS satellites such as this NAVSTAR have been launched since 1978. ...


Comparison with modern technology

Ironically it was largely through additional internal parallelism that conventional CPU designs got faster. Instead of using a heavyweight explicit system like the transputer, modern CPU designs are parallel only at the instruction level, looking at the code being run and then distributing what it can be sure of across a number of internal arithmetic and storage units within the CPU core. This form of parallelism, known as superscalar, has proved more suitable to general purpose computing. Most critically, it and speculative execution delivered a tangible performance increase to existing code. By speeding up existing applications, the classic 'single CPU' microprocessor managed to outrun parallel systems such as the transputer, whose performance benefits only showed up in massive-multiprocessor installations. The mainstream programming languages of the time - Pascal, Fortran, C and later C++ - lacked any intrinsic parallelisation, so this single-CPU parallelism delivered a speedup without the need to rewrite the application. Simple superscalar pipeline. ... In computer science, speculative execution is the execution of code whose result may not actually be needed. ...


Nevertheless, the model of multiple cooperating processors can be found in modern cluster computing systems and supercomputers. Unlike in the proposed transputer architecture, the processing units in these systems are similar to conventional computer servers, using CPUs with an internal superscalar architecture, access to substantial amounts of memory and often disk storage, and conventional operating systems and network interfaces. The software architecture used to marshal the cooperating software processes across the loosely coupled processors in these systems is typically far more heavyweight than that implemented in the transputer architecture. Linux Cluster at Purdue University A computer cluster is a group of locally connected computers that work together as a unit. ... A supercomputer is a computer that leads the world in terms of processing capacity, particularly speed of calculation, at the time of its introduction. ...


The nearest modern equivalent to the transputer link technology is the HyperTransport processor interconnection fabric designed by AMD. Although it is capable of message-passing, HyperTransport is, unlike the transputer link, generally used to implement a shared memory system for implementing a traditional symmetric multiprocessing software architecture. HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency computer bus that was introduced on April 2, 2001 [1]. The HyperTransport Technology Consortium is in charge of promoting and developing HyperTransport technology. ... Advanced Micro Devices, Inc. ... In computer hardware, shared memory refers to a (typically) large block of random access memory that can be accessed by several different central processing units (CPUs) in a multiple-processor computer system. ... Symmetric Multiprocessing, or SMP, is a multiprocessor computer architecture where two or more identical processors are connected to a single shared main memory. ...


A recent intriguing development is the Cell processor architecture designed by Sony, which some of Sony's patent applications seem to show as being designed to be able to run distributed processes at low level in a similar way to that proposed in the transputer architecture. However, this aspect of the Cell design does not seem to have been used in the first implementation of the system, which appears to be more dedicated to using its abilities as a set of parallel DSP engines connected by DMA pipelines, under the control of a conventional core processor. The Cell is a microprocessor design being developed by IBM in cooperation with Toshiba and Sony. ...


As the ability to increase the clock speed of CPU cores appears to have reached a (possibly temporary) limit, there has been renewed interest in multiple-CPUs on a single die, multicore processors. Again, improvements in inter-process communications and synchronisation may be useful here, although the cost of converting existing applications invariably acts as a barrier to change. A multicore processor is a chip with more than one processing units (cores). ...


See also

David May is a British chip designer and computer scientist. ... The Atari Transputer Workstation (also known as ATW-800, or simply ATW) was a workstation class computer released by Atari in the late 1980s. ... IEEE-1355, IEC 14575, or ISC 14575 is a data communications standard, the IEEE Standard for Heterogeneous Interconnect (HIC). ... Meiko Scientific was a supercomputer company founded by members of the design team working on the INMOS Transputer. ... iWarp was an experimental multiprocessing supercomputer developed as a joint project by Intel and Carnegie Mellon University. ...

External links

  • Some technical notes
  • INMOS DSP Databook

  Results from FactBites:
 
INMOS Transputer - Wikipedia, the free encyclopedia (2099 words)
The INMOS Transputer was a pioneering parallel computing microprocessor design of the 1980s from INMOS, a small English company based in Bristol.
INMOS saw them being used for practically everything, from operating as the main CPU for a computer, to acting as a channel controller for disk drives in the same machine.
The Transputer's lack of support for virtual memory inhibited the porting of mainstream variants of the UNIX operating system, though ports of UNIX-like operating systems (such as Minix and Idris from Whitesmiths) were produced.
  More results at FactBites »

 
 

COMMENTARY     


Share your thoughts, questions and commentary here
Your name
Your comments

Want to know more?
Search encyclopedia, statistics and forums:

 


Press Releases |  Feeds | Contact
The Wikipedia article included on this page is licensed under the GFDL.
Images may be subject to relevant owners' copyright.
All other elements are (c) copyright NationMaster.com 2003-5. All Rights Reserved.
Usage implies agreement with terms, 1022, m