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Encyclopedia > Explicitly Parallel Instruction Computing

Explicitly Parallel Instruction Computing (EPIC) is a computing paradigm that began to be researched in the early 1980s resulting in a U.S. patent 4,847,755 (Gordon Morrison, et. al).[1] This paradigm is also called Independence architectures. It was used by Intel and HP in the development of Intel’s IA-64 architecture, and has been implemented in Intel’s Itanium and Itanium 2 line of server processors. The goal of EPIC was to increase the ability of microprocessors to execute software instructions in parallel, by using the compiler, rather than complex on-die circuitry, to identify and leverage opportunities for parallel execution. This would allow performance to be scaled more rapidly in future processor designs, without resorting to ever-higher clock frequencies, which have since become problematic due to associated power and cooling issues. A computing paradigm is a rough categorisation of programming languages based on how their syntax describes the handling of data. ... The 1980s refers to the years from 1980 to 1989. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... HP may refer to: Handley Page Aircraft Company Harry Potter, a series of fantasy novels by British writer J. K. Rowling Hello! Project (H!P), a Japanese pop recording project Hewlett-Packard, a computer and computer peripheral company High Point, North Carolina High potency, a term used in biology, pharmacology... In computing, IA-64 (short for Intel Architecture-64) is a 64-bit processor architecture developed cooperatively by Intel Corporation and Hewlett-Packard (HP), and implemented in the Itanium and Itanium 2 processors. ... Itanium is the brand name for 64-bit Intel microprocessors that implement the Intel Itanium architecture (formerly called IA-64). ... Itanium 2 logo The Itanium 2 is an IA-64 64-bit microprocessor developed jointly by Hewlett-Packard (HP) and Intel, and introduced on July 8, 2002. ... A diagram of the operation of a typical multi-language, multi-target compiler. ... A die in the context of integrated circuits is a small piece of semiconducting material on which a given circuit is fabricated. ... The clock rate is the fundamental rate in cycles per second (measured in hertz) at which a computer performs its most basic operations such as adding two numbers or transferring a value from one processor register to another. ... CPUs (Central processing units) in their various incarnations consume some amount of electric power. ... CPU heatsink with fan attached Heat generated by electronic devices and circuitry must be dissipated to improve reliability and prevent premature failure. ...

Contents

Roots in VLIW

Out-of-order execution and speculative execution have been used successfully for many years to increase the parallel execution of software code in mainstream microprocessors. However, due to the growing complexity of scaling these approaches, the processor industry in the mid-1990s started to re-examine instruction sets which explicitly encode multiple operations per instruction. The basis for such research is VLIW, in which multiple operations are encoded in every instruction, and then processed by multiple execution units. In computer engineering, out-of-order execution, OoOE, is a paradigm used in most high-performance microprocessors in order to make use of cycles that would otherwise be wasted by a certain type of costly delay. ... In computer science, speculative execution is the execution of code whose result may not actually be needed. ... For the band, see 1990s (band). ... A Very Long Instruction Word or VLIW CPU architecture implements a form of instruction level parallelism. ...


One goal of this strategy is to move the complexity of instruction scheduling from the CPU hardware to the software compiler, which can do the instruction scheduling statically (with help of trace feedback information). This eliminates the need for complex scheduling circuitry in the CPU, which frees up space and power for other functions, including additional execution resources. An equally important goal is to further exploit instruction level parallelism (ILP), by using the compiler to find and exploit additional opportunities for parallel execution. Instruction-level parallelism (ILP) is a measure of how many of the operations in a computer program can be dealt with at once. ... Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. ...


VLIW (at least the original forms) has several short-comings that precluded it from becoming mainstream:

  • VLIW instruction sets are not backward compatible between implementations. When wider implementations (more execution units) are built, the instruction set for the wider machines is not backward compatible with older, narrower implementations.
  • Load responses from a memory hierarchy which includes CPU caches and DRAM do not have a deterministic delay until the load response returns to the processor. This makes static scheduling of load instructions by the compiler very difficult.

An instruction set is (a list of) all instructions, and all their variations, that a processor can execute. ... This article or section does not cite its references or sources. ... In computer engineering, an execution unit is a part of a CPU that performs the operations and calculations called for by the program. ... Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ... Dram can mean several things: Dram (unit), an imperial unit of volume Dram, an imperial unit of weight or mass, see avoirdupois and apothecaries system Ottoman dram, a unit of weight, see dirhem Armenian dram, a monetary unit DRAM, a type of RAM Category: ...

Moving beyond VLIW

EPIC architectures add several features to get around the deficiencies of VLIW:

  • Each group of multiple software instructions is called a bundle. Each of the bundles has information indicating if this set of operations is depended upon by the subsequent bundle. With this capability, future implementations can be built to issue multiple bundles in parallel. The dependency information is calculated by the compiler, so the hardware does not have to perform operand dependency checking.
  • A speculative load instruction is used as a type of data prefetch. This prefetch increases the chances for a primary cache hit for normal loads.
  • A check load instruction also aids speculative loads by checking that a load was not dependent on a previous store.

The EPIC architecture also includes a grab-bag of architectural concepts to increase ILP:

  • Predicated execution is used to decrease the occurrence of branches and to increase the speculative execution of instructions. In this feature, branch conditions are converted to predicate registers which are used to kill results of executed instructions from the side of the branch which is not taken.
  • Delayed exceptions (using a Not-A-Thing bit within the general purpose registers) also allow more speculative execution past possible exceptions.
  • Very large architectural register files avoid the need for register renaming.
  • Multi-way branch instructions

The IA-64 architecture also added register rotation - a digital signal processing concept useful for loop unrolling and software pipelining. Branch predication, not to be confused with branch prediction, is a strategy in computer architecture design for mitigating the costs usually associated with conditional branches, particularly branches to short sections of code. ... In computer science, speculative execution is the execution of code whose result may not actually be needed. ... In computer engineering, register renaming refers to a technique used to avoid unnecessary serialization of program operations imposed by the reuse of registers by those operations. ... In computing, IA-64 (short for Intel Architecture-64) is a 64-bit processor architecture developed cooperatively by Intel Corporation and Hewlett-Packard (HP), and implemented in the Itanium and Itanium 2 processors. ... Digital signal processing (DSP) is the study of signals in a digital representation and the processing methods of these signals. ... Wikipedia does not yet have an article with this exact name. ... In computer science, software pipelining is a technique used to optimize loops, in a manner that parallels hardware pipelining. ...


Ongoing research and development

  • The IMPACT project at University of Illinois at Urbana-Champaign, led by Wen-mei Hwu, has been the source of much influential research on this topic.
  • The PlayDoh architecture from HP-labs is another major research project.
  • Gelato.org is an open source development community in which academic and commercial researchers are working to develop more effective compilers for Linux applications running on Itanium servers.

A Corner of Main Quad The University of Illinois at Urbana-Champaign (UIUC, U of I, or simply Illinois), is the oldest, largest, and most prestigious campus in the University of Illinois system. ... Wen-mei Hwu is a professor at University of Illinois at Urbana-Champaign specializing in compilers and reconfigurable computing. ...

See also

A complex instruction set computer (CISC) is a microprocessor instruction set architecture (ISA) in which each instruction can execute several low-level operations, such as a load from memory, an arithmetic operation, and a memory store, all in a single instruction. ... This article does not cite any references or sources. ... A Very Long Instruction Word or VLIW CPU architecture implements a form of instruction level parallelism. ... Elbrus (ЭЛЬБРУС) is the name (after the mountain) of a series of Soviet supercomputer systems developed in Russia by Elbrus MCST and/or ITMiVT since the 1970s; its current models are compatible with U.S.-developed SPARC designs. ...

References

  1. ^ US patent 4847755

External links


  Results from FactBites:
 
Explicitly Parallel Instruction Computing - Wikipedia, the free encyclopedia (563 words)
Explicitly Parallel Instruction Computing ('EPIC) is a computing paradigm that began to be researched in the 1990s.
One goal is to move the complexity of dynamic scheduling of multiple instruction issue from the hardware implementation to the compiler, which can do the instruction scheduling statically (with help of trace feedback information).
predicated execution is used to decrease the occurrences of branches and increase the speculative execution of instructions.
VLIW: old architecture of the new generation (6438 words)
Moreover, the EPIC improves the ability of the compiler to generate plans of execution statically at the expense of various code transitions during compilation which are not correct in the serial architecture.
EPIC was developed exactly to reach a higher degree of parallel instruction computing with an acceptable hardware complexity.
All such instructions can be divided into instructions of operation with a register stack, integer instructions, instructions of comparison and operation with predicates, memory access instructions, jump instructions, multimedia instructions, interregister move instructions, "miscellaneous" instructions (operations with lines and count of bits in a word) and floating-point instructions.
  More results at FactBites »

 
 

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