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Encyclopedia > Clock gating

Clock gating is one of the power-saving techniques used on the Pentium 4 processor. To save power, clock gating refers to activating the clocks in a logic block only when there is work to be done. From the earliest days of the Pentium 4 processor design, power consumption was a concern. The clock gating concept isn't a new one; however, the Pentium 4 processor used this technology to a large extent. Every unit on the chip has a power reduction plan, and almost every Functional Unit Block (FUB) contains clock gating logic. Clock gating can also be used for chip testing. clock gating logic: http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch08/Figure-8.20.gif


The technique of clock gating is used in synchronous circuitry to disable portions of a circuit when they are not actively performing computation. Although asynchronous circuits by definition do not have a "clock", the term "perfect clock gating" is used to illustrate how various clock gating techniques are simply approximations of the data-dependent behavior exhibited by asynchronous circuitry, and that as the granularity on which you gate the clock of a synchronous circuit approaches zero, the power consumption of that circuit approaches that of an asynchronous circuit. An asynchronous circuit is a circuit in which the parts are largely autonomous. ...


Perfect clock gating refers to a property of some classes of asynchronous circuits whereby the circuit only generates logic transitions when it is actively computing. An asynchronous circuit is a circuit in which the parts are largely autonomous. ...


  Results from FactBites:
 
Chip Design Magazine | Tools, Techniques & Methodologies (1928 words)
It reduces power by disabling the clock on registers when the output is not changing.
Since combinational clock gated flops maintain a one to one state mapping with the original RTL, Combinational Equivalence Checking Tools can be used for functional verification.
To eliminate glitching on the clock line, special clock generator cells were added to output of the enable logic.
Power efficient booth multiplier using clock gating - Patent 5661673 (9364 words)
The clock signals used to control the data processing operations and flow of data through the registers and adders are gated so that those registers which are needed for the stage of the multiplication operation being executed are clocked, while the other registers are not enabled.
During the time clock B0 signal 109 is being used to shift the 32 bits loaded into register 108 out to the recoder in groups of 4 bits, clock B signal 107 is used to load the remaining 224 bits of operand B into register 106.
The gating of clock signal 105, 107, and 109 so that they are controlling their respective registers when needed instead of being actively connected at all times reduces the power consumption of multiplier circuit 100.
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