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Encyclopedia > Clock frequency

In synchronous digital electronics, such as most computers, a clock signal is a signal used to coordinate the actions of two or more circuits. A clock signal oscillates between a high and a low state, normally with a 50% duty cycle. In other words, the signal is a square wave. The circuits using the clock signal for synchronization may become active at either the rising or falling edge, or both (see for example DDR SDRAM), of the clock signal.


Most integrated circuits of sufficient complexity require a clock signal in order to synchronize different parts of the chip and to account for propagation delays. As chips get more complex, the problem of supplying accurate and synchronized clocks to all the circuits becomes more and more difficult. The preeminent example of such complex chips is the microprocessor, the central part of modern computers.


The speed of a clock signal in a computer is called the clock rate or clock frequency.






  Results from FactBites:
 
Cross clock domain clocking for a system using two clock frequencies where one frequency is fractional multiple of the ... (7494 words)
This invention relates to circuits and methods for transferring signals across clock domains and particularly to input and output cells for a processor having a core that operates at a frequency that is a half-integer multiple of a bus clock frequency.
Bus signals are commonly synchronized with the rising edges of the bus clock signal, but when the processor clock frequency is a non-integer multiple of the bus clock frequency, the rising edge of the processor clock signal that is closest in time to a rising edge of the bus clock signal may be significantly offset.
A higher-frequency clock signal clocks the latch, and a control circuit enables rising-edge or falling-edge latching depending on whether a rising edge or a falling edge of the higher-frequency clock signal is closest in time to a required edge of a lower-frequency clock signal.
Reference Clock Drivers (1089 words)
The local clock driver also supports an external synchronization source such as a high resolution counter disciplined by a GPS receiver, for example.
When more than one clock driver is supported, it is often the case that each shows small systematic offset differences relative to the rest.
To reduce the effects of jitter when switching from one driver to the another, it is useful to calibrate the drivers to a common ensemble offset.
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