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Encyclopedia > AMD K10

The AMD K10 is AMD's next generation of processors. It had previously been reported as a cancelled project by tech tabloid The Inquirer [1], but was declared by AMD officials that the AMD K10 processor series is the immediate successor to the AMD K8 series of processors (Athlon 64, Opteron, Sempron 64 respectively, and sharing technologies with the Socket S1 Turion 64)[citation needed]. Image File history File links Gnome_globe_current_event. ... “AMD” redirects here. ... A Tech Tabloid is a type of news media that mainly concentrates on technology news: science, IT, semiconductors, telecoms and related issues, but also takes on a less formal and more humorous approach than traditional technology publications such as EE Times or EDN. They are professional in nature, though, rather... This article is about the British technology news website. ... The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... The AMD Opteron was the AMDs x86 server processor line, and the first processors to implement the AMD64 (also known as x86-64) instruction set architecture. ... AMD Sempron Logo Socket-A Sempron 3000+ Sempron is, as of 2005-06, AMDs newest low-end CPU, replacing the (in 2004, when the Sempron was launched) four year old Duron processor and competing against Intels Celeron D processor. ... Socket S1 is the new type of CPU socket predicted to be used by AMD for their new Turion and Athlon 64 Mobile processors. ... For other uses, see Turion. ...

Contents

Nomenclatures

It is commonly perceived that from the time after the use of the codename K8 for the AMD K8 or Athlon 64 processor family, AMD no longer uses K-nomenclatures (originally stood for Kryptonite [2]) since no K-nomenclature naming convention beyond K8 has appeared in official AMD documents and press releases after the beginning of 2005. The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... The Athlon 64 is an eighth-generation, AMD64 architecture microprocessor produced by AMD, released on September 23, 2003. ... This article is about the fictional substance. ... Year 2005 (MMV) was a common year starting on Saturday (link displays full calendar) of the Gregorian calendar. ...


The name "K8L" was first coined by Charlie Demerjian, one of the writers of The Inquirer back in 2005 [3], and was used by the wider IT community as a convenient shorthand [4] along with Stars, as the codenames for desktop line of processors was named under stars or constellations, while according to AMD official documents, the processor family was termed "AMD Next Generation Processor Technology" [5]. This article is about the British technology news website. ...


In a video interview [6], Giuseppe Amato confirmed that the codename is K10.


It was revealed that the codename "K8L" was referred to a low-power version of the K8 family, later named Turion 64, and that K10 was the official codename for the microarchitecture [4] by The Inquirer itself. For other uses, see Turion. ... This article is about the British technology news website. ...


Schedule of launch and delivery

Timeline

Historical information

In 2003, AMD outlined the features for upcoming generations of microprocessors after K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003 [7], the outlined features to be deployed by the next-generation microprocessors are as follows:

However, as of 2006, some of the original outlined features had been abandoned, examples as the high processor clock speed due to thermal limitations, and some others were not implemented, such as threaded architectures [citation needed]. Many programming languages, operating systems, and other software development environments support what are called threads of execution. ... Multiprocessing is traditionally known as the use of multiple concurrent processes in a system as opposed to a single process at any one instant. ... Simple superscalar pipeline. ... In computer science, out-of-order execution is a paradigm used in most high-speed microprocessors in order to make use of cycles that would otherwise be wasted by a certain type of costly delay. ... A vector processor, or array processor, is a CPU design that is able to run mathematical operations on a large number of data elements very quickly. ... In computing, virtualization is a broad term that refers to the abstraction of computer resources. ...


On April 13, 2006, Henri Richard, AMD executive vice president and chief officer for marketing and sales, acknowledged[8] the existence of the new microarchitecture in an interview. is the 103rd day of the year (104th in leap years) in the Gregorian calendar. ... Advanced Micro Devices, Inc. ...


In June 2006, AMD executive vice president Henri Richard had another interview with DigiTimes commented on the upcoming processor developments:

Q: What is your broad perspective on the development of AMD processor technology over the next three to four years?

A: Well, as Dirk Meyer commented at our analysts meeting, we're not standing still. We've talked about the refresh of the current K8 architecture that will come in '07, with significant improvements in many different areas of the processor, including integer performance, floating point performance, memory bandwidth, interconnections and so on. You know that platform still has a lot of legs under it, but of course we're not standing still, and there's a next-generation core that's being worked on. I can't give you more details right now, but I think that what's important is that we're establishing clearly that this is a two-horse race. And as you would expect in a race, sometimes, when one horse is a little bit in front of the other, it reverses the situation. But what's important is that it is a race.

 
— AMD Executive Vice President, Henri Richard, Source: DigiTimes Interview with Henri Richard[9]

Confirmation of time frames

"Barcelona" die shot

On July 21, 2006, AMD President and Chief operating officer (COO) Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of new microprocessors of Revision H under the new microarchitecture is slated for the middle of 2007; and that it will contain a quad core version for servers, workstations, and high-end desktops, as well as a dual core version for consumer Desktops. Some of the Revision H Opterons shipped in 2007 will have a thermal design power of 68 W. Image File history File linksMetadata Size of this preview: 602 × 599 pixelsFull resolution (1326 × 1320 pixel, file size: 833 KB, MIME type: image/jpeg) Die shot of quad-core Barcelona processor from AMD. File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to... Image File history File linksMetadata Size of this preview: 602 × 599 pixelsFull resolution (1326 × 1320 pixel, file size: 833 KB, MIME type: image/jpeg) Die shot of quad-core Barcelona processor from AMD. File history Legend: (cur) = this is the current file, (del) = delete this old version, (rev) = revert to... is the 202nd day of the year (203rd in leap years) in the Gregorian calendar. ... Year 2006 (MMVI) was a common year starting on Sunday of the Gregorian calendar. ... A microprocessor is a programmable digital electronic component that incorporates the functions of a central processing unit (CPU) on a single semiconducting integrated circuit (IC). ... A dual-core CPU combines two independent processors and their respective caches and cache controllers onto a single silicon chip, or integrated circuit. ... This article does not cite any references or sources. ... A computer workstation, often colloquially referred to as workstation, is a high-end general-purpose microcomputer designed to be used by one person at a time and which offers higher performance than normally found in a personal computer, especially with respect to graphics, processing power and the ability to carry... Desktop computer with several common peripherals (Monitor, keyboard, mouse, speakers, microphone and a printer) A desktop computer is a computer made for use on a desk in an office or home and is distinguished from portable computers such as laptops or PDAs. ... The Thermal Design Power (TDP) represents the maximum amount of power the thermal solution in a computer system is required to dissipate. ... For other uses, see Watt (disambiguation). ...


On August 15, 2006, at the launch of the first Socket F (also known as Socket 1207) dual core Opterons, AMD announced that the firm had reached the final design stage (tape-out) of quad-core Opteron parts. The next stages are testing and validation, with sampling to follow after several months.[10] is the 227th day of the year (228th in leap years) in the Gregorian calendar. ... Year 2006 (MMVI) was a common year starting on Sunday of the Gregorian calendar. ... This article or section does not cite any references or sources. ... The AMD Opteron was the AMDs x86 server processor line, and the first processors to implement the AMD64 (also known as x86-64) instruction set architecture. ... In electronics, tape-out is the name of the final stage of the design of an integrated circuit such as a microprocessor, the point at which the description of a circuit is sent for manufacture. ... The AMD Opteron was the AMDs x86 server processor line, and the first processors to implement the AMD64 (also known as x86-64) instruction set architecture. ...


On June 29, 2007, AMD stated that server processors codenamed Barcelona will ship in August 2007, and corresponding server systems from partners will ship in September of the same year.[11] is the 180th day of the year (181st in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ...


On August 13, the reported ship dates for the first Barcelona processors were set for September 10, 2007. They announced the Opteron 2348 and 2350 will have core frequencies of 1.9 GHz and 2.0 GHz and will be priced at $320 and $390. [12]


Internal codenames

As of November 2006, reports leaked the upcoming desktop part codenames Agena, Agena FX,[13] and the core speeds of the parts range from 2.4 GHz - 2.9 GHz respectively, 512 KiB L2 cache each core, 2 MiB L3 cache, using HyperTransport 3.0, with a TDP of 125 W.[14] In recent reports, single core variants (codenamed Spica) and dual core with or without L3 cache (codenamed Kuma and Rana respectively) are available.[13] variants under the same microarchitecture [15]. According to the International Electrotechnical Commission a kibibyte (a contraction of kilo binary byte) is a unit of information or computer storage. ... The three-letter acronym MIB may refer to any of several concepts: Management information base, a computing information repository used (for example) by SNMP In marbles, any marble, but esp. ...


During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server, desktop and mobile processors.[16] For the servers segment, AMD will unveil two new processors based on the architecture codenamed "Barcelona" and "Budapest" for more than 1-way and 1-way servers respectively [16]. Desktops will see an overhaul of the entire processor lineup. Single-core "Lima" built on 65 nm fabrication process node the single-core processors will arrive in Q1 2007 while Sparta, the Sempron 65 nm process update, will come in Q2 2007. For the second half of 2007, HyperTransport 3.0 and Socket AM2+ will be unveiled, which are designed for the specific implementation of the aforementioned consumer quad core desktop chip series, with naming convention changes from city names (up to middle of 2007) to stars or constellations after that, such as Agena; in addition, the AMD Quad FX platform and its immediate successor will support the high end enthusiast dual-processor versions of the chip, codenamed as Agena FX [13], updates the processors line for AMD Quad FX platform. As with the server chips codenamed Barcelona, the new desktop quad core series will feature a shared L3 cache, 128-bit floating point (FP) units and an enhanced microarchitecture. Agena will be the native quad-core processor for the desktop. Kuma, a dual-core variant will follow on in Q3 while Rana, the dual-core version with no shared L3 cache is expected at the end of the year [13]. is the 348th day of the year (349th in leap years) in the Gregorian calendar. ... Year 2006 (MMVI) was a common year starting on Sunday of the Gregorian calendar. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... This article or section does not adequately cite its references or sources. ... The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron processors (CPUs) into a single motherboard for a total of four physical cores [1]. This is a type of dual processor setup, where... The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron processors (CPUs) into a single motherboard for a total of four physical cores [1]. This is a type of dual processor setup, where...


Subsequent product launches

More information about the upcoming chip codenamed "Montreal" on the server roadmap [17] using MCM technique of two "Shanghai" cores with a total of 12 MiB L3-cache [18] codenamed AMD K10.5 [19]. The desktop variant for Shanghai is codenamed Ridgeback [20]. Afterwards is the release of products based on the Bulldozer cores, which is optimized with integrated graphics core (AMD Fusion) or octal-core architecture (codenamed Sandtiger), and Bobcat core, optimized for low-power operations. ... Bulldozer is the codename AMD has given to one of the next-generation CPU cores after K10 microarchitecture for the companys M-SPACE design methodology, with the core specifically aimed at 10 Watts to 100 Watts TDP computing products. ... AMD Fusion is the codename for a future next-generation microprocessor design and the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of todays GPUs into a single package. ... Codenamed Bobcat, is a processor designed by AMD, which was revealed during the a speech address from AMD executive vice-president Henri Richard in Computex 2007 held in Taiwan, no specific release dates was given but rumours and speculations forecast a post-2008 launch [1]. The Bobcat processor was a...


Change of model nomenclatures

During Computex 2007 in early June, new information regarding the naming schemes of upcoming AMD microprocessors emerged. Additional letters indicating both performance and power envelope will precede the 4 digit model number [21].


The model numbers of the new line of processors were apprently changed from the PR ratings used by its predecessors, the Athlon 64 series processors (except Phenom FX series, being suggested to follow the nomenclature of Athlon 64 FX series). As reported by DailyTech [22], the model numbers are in alpha-numeric format as AA-@### where AA are alphabetical letters, the first letter indicating the processor class and the second indicating the typical TDP power envelope. The character @ is the series indicator, which varies by branding (see below table), and the last three characters (###) are the model number, with higher numbers indicating greater performance. The PR rating system was developed by AMD in the mid-1990s as a method of comparing their x86 processors to those of rival Intel. ... The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... Phenom (pronounced as IPA: as in the word phenomenon, IPA:) is the AMD desktop processor line based on the K10 microarchitecture. ... The Athlon 64 FX is an AMD K8 series processor targeted at enthusiasts. ... The Thermal Design Power (TDP) represents the maximum amount of power the thermal solution in a computer system is required to dissipate. ...


Not much information was known about the details of the model numbers, but the processors will be divided into three segments: Premium, Intermediate, and Value. Premium segment model numbers have processor class "G", Intermediate segment "B", and Value level "L", as discovered on the web from the AsRock website [23]. Similarly, three levels of TDP, "more than 65W", "65W", and "less than 65W", are indicated by the letters "P", "S", and "E" respectively [22]. Details can be found in the tables below.

Processor segment indicator
Segment Indicator
Premium G
Intermediate B
Value L
TDP indicator
Class power envelope(TDP) Indicator
Premium (more than 65 W) P
Standard (65 W) S
Energy Efficient (less than 65 W) E
Series number
Processor series Indicator
Phenom X4 7
Phenom triple-core processors ?
Phenom X2 6
Athlon X2 2
Sempron 1

The Thermal Design Power (TDP) represents the maximum amount of power the thermal solution in a computer system is required to dissipate. ... For other uses, see Watt (disambiguation). ... For other uses, see Watt (disambiguation). ... For other uses, see Watt (disambiguation). ...

Live demonstrations

On November 30, 2006, AMD live demoed the native quad core chip known as "Barcelona" for the first time in public,[24] while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than Intel Xeon 5355 processor codenamed Clovertown [25]. More details regarding this first revision of the next generation AMD microprocessor architecture have surfaced on the web recently including their clock speeds.[26][27] is the 334th day of the year (335th in leap years) in the Gregorian calendar. ... Year 2006 (MMVI) was a common year starting on Sunday of the Gregorian calendar. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article is about the Intel microprocessor. ...


On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed Clovertown dual-processor (2P) quad-core processors [28]. The expected performance of floating point per core would be approximately 1.8 times that of the K8 family, at the same clock speed [29]. The Intel Core microarchitecture is a multi-core processor microarchitecture unveiled by Intel in Q1 2006. ... A floating-point number is a digital representation for a number in a certain subset of the rational numbers, and is often used to approximate an arbitrary real number on a computer. ...


However, LINPACK benchmarks show that in terms of FLOPS, the Barcelona's peak performance (64 GFLOPS [1]) is only slightly faster than that of the Clovertown X5355 (63.5 GFLOPS [2]). LINPACK is a software library for performing numerical linear algebra on digital computers. ...


On May 10, 2007, AMD held a private event demonstrating the upcoming processors codenamed Agena FX and chipsets, with one demonstrated system being AMD Quad FX platform with one Radeon HD 2900 XT graphics card on the upcoming RD790 chipset, the system was also demonstrated real-time converting a 720p video clip into another undisclosed format while all 8 cores were maxed at 100% by other tasks. [30] is the 130th day of the year (131st in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron processors (CPUs) into a single motherboard for a total of four physical cores [1]. This is a type of dual processor setup, where... The graphics processing unit (GPU) codenamed R600 is the foundation of the Radeon HD 2000 series and the FireGL 2007 series video cards developed by ATI Technologies. ... A video card, (also referred to as a graphics accelerator card, display adapter, graphics card, and numerous other terms), is an item of personal computer hardware whose function is to generate and output images to a display. ... RD700 series is a chipset series made by ATI and is targeted to launch between the end of 2007 to the first half of 2008. ... JOHN HERMAN SUCKS FAT DICK ...


Sister microarchitecture

Also due in a similar timeframe will be a sister microarchitecture, which will focus on lower power consumption chips in mobile platforms as well as small form factor features. This microarchitecture will contain specialized features such as mobile optimized crossbar switch and memory controller and other on-die components; link power management for HyperTransport 3.0; and others. At that time, AMD simply dubbed it "New Mobile Core", without giving a specific codename. Microarchitecture consists of a set of microprocessor design techniques used to implement the instruction set (including microcode, pipelining, cache systems, etc. ... The Shuttle XPC SN25P Small form factor (SFF) computers are housed in smaller cases than typical desktop computers. ... A crossbar switch is one of the principal architectures used to construct switches of many types. ... This article or section does not adequately cite its references or sources. ... Integrated circuit of Atmel Diopsis 740 System on Chip showing memory blocks, logic and input/output pads around the periphery Microchips with a transparent window, showing the integrated circuit inside. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... A code name or cryptonym is a word or name used clandestinely to refer to another name or word. ...


On the December 2006 analyst day, Executive vice president Marty Seyer announced the new mobile core codenamed Griffin to be launched in 2008 with inherented power optimizations technologies from the K10 architecture, but based on a K8 design [31]. Codenamed Griffin, is the first internal project from AMD for a new line of processors solely for the mobile platform, based on the Athlon 64 (K8) architecture with some specific architectural enhancements similar to upcoming Opteron processors aimed at lower power consumption and longer battery life. ...


Iterations of the release

In late 2007 to second quarter of 2008, there will be a modification to the core to be fabricated at 45 nm process node [32], with enhancements such as FB-DIMM support, Direct Connect Architecture 2.0, enhanced Reliability, Availability and Serviceability (RAS), and probably more for the processor die. The platform will also add support for I/O Virtualization, PCI Express 2.0, 10 Gigabit NIC, larger caches, and more. The 45 nanometer (45 nm) process is the next milestone (to be commercially viable in late 2006 to early 2007) in semiconductor manufacturing and fabrication. ... FB-DIMM Architecture Fully Buffered DIMM (or FB-DIMM) is a memory technology which can be used to increase reliability, speed and density of memory systems. ... The Direct Connect Architecture is the I/O architecture of the Athlon64 and Opteron microprocessors from AMD. It consists of the combination of three elements: The microprocessor is directly connected to DRAM memory through an integrated memory controller. ... PCI Express (formerly known as 3GIO for 3rd Generation I/O, not to be mistaken with PCI-X) is an implementation of the PCI computer bus that uses existing PCI programming concepts and communications standards, but bases it on a much faster serial communications system. ... A network card, network adapter or NIC (network interface controller) is a piece of computer hardware designed to allow computers to communicate over a computer network. ...


However, reports have suggested that FB-DIMM support had been dropped from future roadmaps of the majority of AMD products since popularity is low [33][34]. Also, FB-DIMM's future as an industry standard had been called into question. FB-DIMM Architecture Fully Buffered DIMM (or FB-DIMM) is a memory technology which can be used to increase reliability, speed and density of memory systems. ...


An article published by The Inquirer corroborates the earlier reports of the timeline (as cited in this article). According to the report, there will be three iterations of the server processor core: one named Barcelona, due in Q2 of 2007, with new CPU core components as well as the microarchitecture, but built on the old HyperTransport 2.0 infrastructure; the second is Budapest for single socket systems using socket AM2+ or socket AM3, with HyperTransport 3.0; and the third, codenamed Shanghai is an update of the server chip, based on 45 nm process [35], probably also with HyperTransport 3.0 and DDR3 implementation, due in Q1-Q2 2008.[36] This article is about the British technology news website. ... This article or section does not adequately cite its references or sources. ... The Socket AM3, is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ...


AMD, on September 17, 2007, announced [37] that a three core (triple-core) processor will also be released under the Phenom brand lineup, codenamed Toliman. Reports has that the processor was not a quad-core processor with one core disabled, rather be another design, directly benefitted from the Direct Connect Architecture [38], while some believed that this product is benefitted from ATI technologies to add fuses to the quad-core processor and shutting down one of the four cores to become a triple-core processor, which the technique has been popular for making one or more mainstream GPU cores from a single high-end GPU core by blowing out parts of the circuit to save R&D costs while targeting more markets some time ago. The triple-core processor still see the same specifications for quad-core variants, the naming of the processor lineup, according to the AMD branding scheme, will presumably named as Phenom X3, the processor line will be focused on what AMD called the fourth market segment or the "High-end Mainstream" segement beside Value, Mainstream and Performance segments in an interview with BetaNews, which the targeted customers of the processors are "those who are willing to pay more for more performance but not required for too much processing power as required by gamers and system builders [39][40], while there are single core (Sempron) variants for low-end market, and dual-core (Athlon X2 and Phenom X2) variants for mid-range market, and quad-core (Phenom X4 and Phenom FX) variants should be seen in the high-end market at the same timeframe. A dual-core CPU combines two independent processors and their respective caches and cache controllers onto a single silicon chip, or integrated circuit. ... The Direct Connect Architecture is the I/O architecture of the Athlon64 and Opteron microprocessors from AMD. It consists of the combination of three elements: The microprocessor is directly connected to DRAM memory through an integrated memory controller. ...


Further in 2008, AMD will introduce Deneb FX for the replacement for the AMD Quad FX platform, as well as Deneb for the mainstream. Propos and Regor will also replace Kuma and Rana in the lower market segments. Socket AM2+ being named in the late 2006 might actually have been the original AM3 socket, but as naming conventions changed, so that the next generation of consumer desktop socket capable of DDR3 will be socket AM3. [41] The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron processors (CPUs) into a single motherboard for a total of four physical cores [1]. This is a type of dual processor setup, where... This article or section does not adequately cite its references or sources. ... The Socket AM3, is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ...


Features

Fabrication technology

Possible die size of quad-core K10
Possible die size of quad-core K10

AMD will introduce the microprocessors manufactured at 65 nm feature width using Silicon-on-insulator (SOI) technology, since the release of K10 coincides with the volume ramp of this manufacturing process [42]. The servers will be produced for Socket F or Socket F+ (1207) infrastructure, the only server socket on AMD's near-term roadmap; the desktop parts will come on Socket AM2 or Socket AM2+. Image File history File linksMetadata Download high-resolution version (1750x550, 729 KB) Own compilation of public images. ... Image File history File linksMetadata Download high-resolution version (1750x550, 729 KB) Own compilation of public images. ... The 65 nanometer (65 nm) process is the next milestone as of 2005 in semiconductor manufacturing and fabrication. ... Silicon on insulator (SOI) is a layered structure consisting of a thin layer of silicon, from 50 nm to 100 µm, which is created on an insulating substrate, which is usually sapphire or silicon with an insulating layer of silicon dioxide(SiO2) 80 nm to 3 µm thick on its... This article or section does not cite any references or sources. ... Socket F+ is a CPU Socket for AMD server processors from the K10 series. ... The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... This article or section does not adequately cite its references or sources. ...


AMD announced during the Technology Analyst Day [43] that the use of Continuous Transistor Improvement (CTI) and Shared Transistor Technology (STT) would finally lead to the implementation of Silicon-Germanium-On-Insulator (SGoI) on 65 nm process CPUs [44]. It has been suggested that this article or section be merged with SiGe. ... The 65 nanometer (65 nm) process is the next milestone as of 2005 in semiconductor manufacturing and fabrication. ...


Supported DRAM standards

The K8 family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die memory controller (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. DDR2 RAM introduces some additional latency over traditional DDR RAM since the DRAM is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on CAS Latency alone are not sufficient. For example, Socket AM2 processors are known to demonstrate similar performance using DDR2 SDRAM as Socket 939 processors that utilize DDR-400 SDRAM. K10 processors support DDR2 SDRAM rated up to DDR2-1066 (1066 MHz) [45]. The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... SDRAM latency refers to the delays incurred when a computer tries to access data in SDRAM. SDRAM latency is often measured in memory bus clock cycles. ... This article or section does not adequately cite its references or sources. ... “DDR2” redirects here. ... DDR SDRAM or double-data-rate synchronous dynamic random access memory is a type of memory integrated circuit used in computers. ... Dynamic random access memory (DRAM) is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. ... This article or section is in need of attention from an expert on the subject. ... The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... Socket 939 was introduced by AMD in June 2004 to supersede the previous Socket 754 for Athlon 64 processors. ... “DDR2” redirects here. ...


Higher computational throughput

It was also reported by several sources (such as AnandTech, The Inquirer and Geek.com) that the microprocessors implementing the microarchitecture will feature a doubling in the width of SSE execution units in the cores. With the help of major improvements in the memory subsystem (such as load re-ordering and improved prefetch mechanisms) as well as the doubled instruction fetch and load, it is expected to increase the suitability of the processor to scientific and high-performance computing tasks and potentially improve its competitiveness with Intel's Xeon, Core 2, Itanium 2 and other contemporary microprocessors. AnandTech. ... This article is about the British technology news website. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... “CPU” redirects here. ... Intel Corporation (NASDAQ: INTC, SEHK: 4335), founded in 1968 as Integrated Electronics Corporation, is an American multinational corporation that is best known for designing and manufacturing microprocessors and specialized integrated circuits. ... This article is about the Intel microprocessor. ... The Core 2 brand refers to a range of Intels consumer dual-core and quad-core (2x2) 64-bit x86 CPUs based on the Intel Core microarchitecture, which derived from the 32-bit dual-core Yonah laptop processor. ... Itanium 2 logo The Itanium 2 is an IA-64 64-bit microprocessor developed jointly by Hewlett-Packard (HP) and Intel, and introduced on July 8, 2002. ...


Many of the improvements in computational throughput of each core are listed below. In communication networks, throughput is the amount of digital data per time unit that is delivered over a physical or logical link, or that is passing through a certain network node. ...


Characteristics of the microarchitecture

K10 architecture.
K10 single core with overlay description
K10 single core with overlay description

[46] Image File history File links AMD_K10_arch. ... Image File history File links AMD_K10_arch. ... Image File history File links Metadata No higher resolution available. ... Image File history File links Metadata No higher resolution available. ...

  • Form factors
  • Instruction set additions and extensions
    • New bit-manipulation instructions: Leading Zero Count (LZCNT) and Population Count (POPCNT)
    • New SSE instructions named as SSE4a: combined mask-shift instructions (EXTRQ/INSERTQ) and scalar streaming store instructions (MOVNTSD/MOVNTSS). These instructions are not found in Intel's SSE4
    • Support for unaligned SSE load-operation instructions (which formerly required 16-byte alignment)[48]
  • Execution pipeline enhancements
    • 128-bit wide SSE units
    • Wider L1 data cache interface allowing for two 128-bit loads per cycle (as opposed to two 64-bit loads per cycle with K8)
    • Lower integer divide latency
    • 512-entry indirect branch predictor and a larger return stack (size doubled from K8) and branch target buffer
    • Side-Band Stack Optimizer, dedicated to perform increment/decrement of register stack pointer
    • Fastpathed CALL and RET-Imm instructions (formerly microcoded) as well as MOVs from SIMD registers to general purpose registers
  • Integration of new technologies onto CPU die:
    • Four processor cores (Quad-core)
    • Split power planes for CPU core and memory controller/northbridge for more effective power management, first dubbed Dynamic Independent Core Engagement or D. I. C. E. by AMD and now known as Enhanced PowerNow!, allowing the cores and northbridge (integrated memory controller) to scale power consumption up or down independently [49].
    • Shutting down portions of the circuits in core when not in load, named "CoolCore" Technology.
  • Improvements in the memory subsystem:
    • Improvements in access latency:
      • Support for re-ordering loads ahead of other loads and stores
      • More aggressive instruction prefetching, 32 bytes instruction prefetch as opposed to 16 bytes in K8
      • DRAM prefetcher for buffering reads
      • Buffered burst writeback to RAM in order to reduce contention
    • Changes in memory hierarchy:
      • Prefetch directly into L1 cache as opposed to L2 cache with K8 family
      • 32-way set associative L3 victim cache sized at least 2 MiB, shared between processing cores on a single die (each with 512 KiB of independent exclusive L2 cache), with a sharing-aware replacement policy.
      • Extensible L3 cache design, with 6 MiB planned for 45 nm process node, with the chips codenamed Shanghai.
    • Changes in address space management:
      • Two 64-bit independent memory controllers, each with its own physical address space; this provides an opportunity to better utilize the available bandwidth in case of random memory accesses occurring in heavily multi-threaded environments. This approach is in contrast to the previous "interleaved" design, where the two 64-bit data channels were bounded to a single common address space.
      • Larger Tagged Lookaside Buffers; support for 1 GiB page entries and a new 128-entry 2 MiB page TLB
      • 48-bit memory addressing to allow for 256 TiB memory subsystems
      • Memory mirroring, data poisoning support and Enhanced RAS
      • Nested page tables for AMD-V virtualization technology, claimed to have decreasing world switch time by 25%.
  • Improvements in system interconnect:
    • HyperTransport retry support
    • Support for HyperTransport 3.0, with HyperTransport Link unganging which creates 8 point-to-point links per socket.
  • Platform-level enhancements with additional functionality:
    • Five p-states allowing for automatic clock rate modulation
    • Increased clock gating
    • Official support for coprocessors via HTX slots and vacant CPU sockets through HyperTransport: Torrenza initiative.

This article or section does not adequately cite its references or sources. ... Socket F+ is a CPU Socket for AMD server processors from the K10 series. ... The AMD Quad FX platform is an AMD platform targeted at enthusiasts which allows users to plug two Socket F Athlon 64 FX or 2-way Opteron processors (CPUs) into a single motherboard for a total of four physical cores [1]. This is a type of dual processor setup, where... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... The Socket AM2, renamed from Socket M2 (to prevent using the same name as Cyrix MII processors), is a CPU socket designed by AMD for desktop processors, including the performance, mainstream and value segments. ... This article or section does not cite any references or sources. ... In computer science, an instruction typically refers to a single operation of a processor within a computer architecture. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... SSE4, also known by its Intel code name Tejas New Instructions (TNI), is the fourth iteration of the SSE instruction set. ... SSE (Streaming SIMD Extensions, originally called ISSE, Internet Streaming SIMD Extensions) is a SIMD (Single Instruction, Multiple Data) instruction set designed by Intel and introduced in 1999 in their Pentium III series processors as a reply to AMDs 3DNow! (which had debuted a year earlier). ... In computer architecture, a branch predictor is the part of a processor that determines whether a conditional branch in the instruction flow of a program is likely to be taken or not. ... This article does not cite any references or sources. ... In Computer architecture, instruction prefetch is a common technique used in modern microprocessors to speed up the execution of a program by reducing wait states. ... In Computer architecture, instruction prefetch is a common technique used in modern microprocessors to speed up the execution of a program by reducing wait states. ... The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... Diagram of a CPU memory cache A CPU cache is a cache used by the central processing unit of a computer to reduce the average time to access memory. ... The 45 nanometer (45 nm) process is the next milestone (to be commercially viable in late 2006 to early 2007) in semiconductor manufacturing and fabrication. ... A mebibyte (a contraction of mega binary byte) is a unit of information or computer storage, abbreviated MiB. 1 MiB = 220 bytes = 1,048,576 bytes = 1,024 kibibytes 1 MiB = 1024 (= 210) kibibytes (KiB), and 1024 MiB equal one gibibyte (GiB). ... The introduction to this article provides insufficient context for those unfamiliar with the subject matter. ... IBM originated, mainly computer hardware engineering term. ... x86 virtualization is the method by which the x86 processor architecture is virtualized. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... Torrenza is a technology developed by AMD that paves the way for specialised coprocessors to run in spare CPU sockets on multiway CPU systems. ...

Successor

Codenamed "Fusion" is a CPU technology furthering the trend of continued system component integration onto CPU die (which was initiated by K8 with integrated System Request Queue (SRQ), cross-bar switch, memory controller as well as HyperTransport links), planned beyond these two aforementioned families of products, and will be due in late 2008 or sometime in 2009, the Fusion products will see new processor cores, codenamed "Bulldozer" and "Bobcat" incorporated into the die. AMD Fusion is the codename for a future next-generation microprocessor design and the product of the merger between AMD and ATI, combining general processor execution as well as 3D geometry processing and other functions of todays GPUs into a single package. ... The AMD K8 generation of CPUs is the successor to the AMD K7 generation of CPUs. ... HyperTransport logo HyperTransport (HT), formerly known as Lightning Data Transport (LDT), is a bidirectional serial/parallel high-bandwidth, low-latency point to point link that was introduced on April 2, 2001. ... 2008 (MMVIII) will be a leap year starting on Tuesday of the Gregorian calendar. ... 2009 (MMIX) will be a common year starting on Thursday of the Gregorian calendar. ... Bulldozer is the codename AMD has given to one of the next-generation CPU cores after K10 microarchitecture for the companys M-SPACE design methodology, with the core specifically aimed at 10 Watts to 100 Watts TDP computing products. ... Codenamed Bobcat, is a processor designed by AMD, which was revealed during the a speech address from AMD executive vice-president Henri Richard in Computex 2007 held in Taiwan, no specific release dates was given but rumours and speculations forecast a post-2008 launch [1]. The Bobcat processor was a...


Media discussions

Note: These media discussions are sorted by dates of publishing in ascending orders.

  • "AMD CTO speaks about future AMD technologies", AnandTech, October 14, 2005. 
  • "AMD outlines Future Goals (mostly non-specific at this time)", TechReport, October 17, 2005. 
  • "AMD eyes Z-RAM for dense caches", CNet News.com, January 20, 2006. 
  • "AMD licenses Z-RAM", SlashDot, January 21, 2006. 
  • "AMD's K8L to double FPU units in 2007", Geek.com, February 24, 2006. 
  • "Rev G. and H. AMD64 chips Preliminary information", The Inquirer, March 3, 2006. 
  • "Interview with Henri Richard (Part 2)", DigiTimes, March 14, 2006. 
  • "AMD demonstrates Hardware Coprocessor Offload", LinuxElectrons, 20 March 2006. 
  • "Implementation of FPGA through coherent HTT", The Inquirer, March 26, 2006. 
  • "AMD's K8L 65 nm core due H1 07", Reg Hardware, April 4, 2006. 
  • "An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm and AM2 Performance", AnandTech, April 4, 2006. 
  • "Fab36 substantially converted to 65 nm by mid-2007", AnandTech, April 4, 2006. 
  • "AMD shows off details of K8L", The Inquirer, May 16, 2006. 
  • "AMD's K8L and 4x4 Preview", RealWorldtech, June 2, 2006. 
  • "AMD K8L and 4X4 Technologies", ArsTechnica, June 2, 2006. 
  • "AMD Quad-Core K8L & 4x4 Details", Pure OverClock, June 3, 2006. 
  • "Socket AM2 Forward Compatible With AM3 CPUs", DailyTech, July 6, 2006. 
  • "K8L on schedule, due for release as early as Q1 07", The Inquirer, July 11, 2006. 
  • "GNU binutils support for the new K10 instructions", SourceWare.org, July 13, 2006. 
  • "AMD Executives Confirm K8L to Arrive in Mid-2007", X-bit labs, July 21, 2006. 
  • "AMD To Demo K8L By Year End", moneycontrol.com, July 23, 2006. 
  • "AMD intros new Opterons and promises 68 W quad-core CPUs", tgdaily.com, August 15, 2006. 
  • "Next-Generation AMD Opteron Paves The Way For Quad-Core", crn.com, August 15, 2006. 
  • "AMD's Next Generation Microarchitecture Preview: from K8 to K8L", X-bit labs, August 21, 2006. 
  • "AMD quad cores: the whole story unfolded", The Inquirer, September 16, 2006. 
  • "AMD reinvents the x86", InfoWorld, February 7, 2007. 
  • "Inside Barcelona: AMD's Next Generation", RealWorldTech, May 16, 2007. 

References

  1. ^ AMD's K10 is delayed or dead
  2. ^ News.com report, retrieved August 22, 2007
  3. ^ The Inquirer report
  4. ^ a b Valich, Theo. "AMD explains K8L misnomer", The Inquirer. Retrieved on 2007-03-16. 
  5. ^ Official Announcement of "AMD Next Generation Processor Technology"
  6. ^ Video interview of Giuseppe Amato (AMD's Technical Director, Sales and Marketing EMEA) in February 2007]
  7. ^ Microprocessor Forum 2003 presentation slide
  8. ^ Hall, Chris. Re-defining microprocessors: Q&A with AMD’s Henri Richard. DigiTimes.com. Retrieved on 2007-03-18.
  9. ^ AMD's vision for next few years - an interview with Henri Richard
  10. ^ "Next-Generation AMD Opteron Paves The Way For Quad-Core", crn.com, 15 August 2006. 
  11. ^ "AMD to Ship Industry’s First Native x86 Quad-Core Processors In August", amd.com, 29 June 2007. 
  12. ^ "AMD to launch two Barcelona-based processors in September", tgdaily.com, 13 August 2007. 
  13. ^ a b c d "AMD processor roadmaps for 2007", Tracking AMD, 31 December 2006. 
  14. ^ "AMD Quad-Core Altair upcoming in 2007 Q3", HKEPC, 3 October 2006. 
  15. ^ "AMD to enter K10 era in 2H 2007", HKEPC, 4 October 2006. 
  16. ^ a b "06A-DayMartySeyer.pdf 2006 Analyst Day Slides (Roadmaps for server and mobile", AMD. 
  17. ^ The Inquirer report
  18. ^ FudZilla report
  19. ^ FudZilla report
  20. ^ Fudzilla report, retrieved August 1, 2007
  21. ^ "How to decipher AMD's new CPU naming code", Gadget Lab, 2007-06-04. 
  22. ^ a b DailyTech report
  23. ^ XTReview image: AsRock BIOS 1.40 support Athlon X2 BE-xxxx and Sempron LE-xxxx processors
  24. ^ "AMD Demonstrates Its Quad Core Server Chips", CNET.com, 30 November 2006. 
  25. ^ "AMD Demonstrates Barcelona; The First True, Native Quad Core Opteron", legitreviews.com, 30 November 2006. 
  26. ^ "Quick Look at AMD Quad Core Barcelona", arstechnica.com. 
  27. ^ The Inquirer article
  28. ^ "AMD Expects Quad Core Barcelona to Outperform Clovertown by 40%", dailytech.com, 25 January 2007. 
  29. ^ "Go to 'Barcelona' over 'Cloverton'", CNET.com, 23 January 2007. 
  30. ^ TGDaily report
  31. ^ "AMD updates Opteron, Turion roadmaps", informationweek.com, 14 December 2006. 
  32. ^ "AMD Outlines Quad Core Computing", www.pcpro.co.uk, 19 September 2006. 
  33. ^ "Intel Pulls Back from FB-DIMM", inquirer.net, 7 September 2006. 
  34. ^ "No Shocker Here", legitreviews.com, 15 September 2006. 
  35. ^ DailyTech report
  36. ^ "AMD Quad Cores: The Whole Story Unfolded", inquirer.net, 16 September 2006. 
  37. ^ AMD announcement, retrieved September 17, 2007
  38. ^ X-Bit Labs report, retrieved September 17, 2007
  39. ^ BetaNews report, retrieved September 17, 2007
  40. ^ BetaNews interview, retrieved September 17, 2007
  41. ^ "AMD: 45nm, DDR3, and AM3 in 2008", dailytech.com, 2 May 2007. 
  42. ^ "An AMD Update: Fab 36 Begins Shipments, Planning for 65 nm process and AM2 Performance", AnandTech, April 4, 2006. 
  43. ^ 2006 AMD Analyst Day 2006 page
  44. ^ Ostrander, Daryl. 2006 Technology Analyst Day Slides. Advanced Micro Devices. Retrieved on 2007-03-19.
  45. ^ "AMD’s next-generation Star supports DDR2-1066 & SSE4a", HKEPC Hardware. Retrieved on 2007-03-19. 
  46. ^ Shimpi, Anand. "Barcelona Architecture: AMD on the Counterattack", AnandTech. Retrieved on 2007-03-18. 
  47. ^ "AMD Quad-Core Altair upcoming in 2007 Q3", HKEPC, 3 October 2006. 
  48. ^ Case, Loyd. "AMD Unveils Barcelona Quad-Core Details", Ziff Davis. Retrieved on 2007-03-18. 
  49. ^ "AMD Next Generation Processor Technology Slides", HardOCP, 22 August 2006. 

Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... March 16 is the 75th day of the year (76th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 77th day of the year (78th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 78th day of the year (79th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 78th day of the year (79th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 77th day of the year (78th in leap years) in the Gregorian calendar. ... Year 2007 (MMVII) is the current year, a common year starting on Monday of the Gregorian calendar and the AD/CE era. ... is the 77th day of the year (78th in leap years) in the Gregorian calendar. ... [H]ard|OCP (Hardware Overclockers Comparison Page) is an online magazine that offers news, reviews, and editorials that relate to computer hardware, software, modding, overclocking and cooling, owned and operated by Kyle Bennett. ...

External links

  • AMD Official Website
  • AMD Quad-core processors introduction
  • DarkVision Hardware: AMD talks about K9, K10 future innovations
  • Next-Generation AMD Opteron™ Processors Introduced with Record OEM Design Wins and Native Quad-Core Upgrade Path (Official AMD press release on 15 August 2006)
  • PC Watch report about K10 based on AMD Technology Analyst Day 2004 and 2005 (Japanese)
  • PC Watch report about K10 based on Slides presented in Microprocessor Forum 2003 (Japanese)
  • Slides of AMD 2006 Technology Analyst Day: Official Introduction of K10 MicroarchitecturePDF (2.17 MiB)
  • Software Optimization Guide for AMD Family 10h Processors
  • TechReport: AMD outlines Future Goals
  • TweakTown Discussions (2003)
  • X-bit labs: AMD K10 Micro-Architecture
  • Quad-Core SPEC Benchmark Analysis

  Results from FactBites:
 
AMD K10 - Wikipedia, the free encyclopedia (361 words)
The AMD K10 is AMD's next generation of processor.
With this in mind, the K10 could prove to be a surprising chip, looking much more like a classic RISC processor than has traditionally been the case with x86 systems, although the AMD64 instruction set is still a CISC instruction set.
AMD's K10 Is delayed or dead (The Inquirer) [1]
  More results at FactBites »

 
 

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