Since 2002 and up to 2004, the 90 nanometer (90 nm) process has been a buzzword in the electronic, the LSI and semiconductor manufacturing, and fabrication industries. "Going beyond 90 nm" represents a breakthrough and a milestone. Related industries, such as the FPGA, network chip, DSP, flash memory chip and nanotechnology industries are also affected and are monitoring 90_nanometer trends as of 2004. Among the companies who have adopted and disclosed their 90 nanometer processes, but taking different approaches, are Intel, IBM, Texas Instruments Inc., Motorola, Fujitsu, TSMC. A majority of these companies made their disclosures in August of 2002. The 90 nanometer process refers to the width of the smallest circuit wires on the chip. The actual features on 90 nanometer chips can be quite smaller, down to around 45 nanometers.
The 90 nanometer point represents a breakthrough or milestone in the size of circuits in LSI, semiconductor manufacturing and fabrication. It is a logical effect of Moore's law. The industrial standard before this was the 0.13 micrometre (130 nm) process. Techniques developed in the 130 nm process where fine-tuned and applied in the 90 nanometer. The next milestone is the 65 nm. The smaller size increased circuit 'real estate' and speed. Smaller processor gates are the immediate benefit of a smaller semiconductor. The narrower a gate is, the faster the gate can be switched from an "on" position to an "off" position, increasing the maximum clock speed of the chip.
As semiconductor technology drops to below 90 nm, however, the number of problems increases and there are only minimal possible improvements. Among the biggest stumbling blocks to 90 nm and finer linewidths is design for manufacturability, which includes optical proximity correction (OPC) and phase-shift technologies as well as increasing attention to yield optimization. Interconnect delays increase, leading to timing closure problems. Increased power consumption raises the heat output, and reduced feature size causes increased electromagnetic interference, more burnt tracks, more accidental interconnects and more unwanted capacitance. Because of their astonishingly small size, the walls between the wires are thin enough to allow electrons to leap between wires. This is called leakage. Some companies are attempting to solve this leakage problem by employing a technique called silicon on insulator (SOI). During the manufacturing process, a thin layer of oxide is applied to the silicon wafer, which acts as insulating material to keep electrons inside of the chip's structures.
The 90 nanometer process has an effect on circuit design methodology itself. Circuits used to be manually designed, but the large amount of 'real estate' in circuit space made available by the 90-nanometer process, plus the huge demand for a significant amount of functionality and sophistication, has forced design engineers to use Electronic Design Automation tools. Verilog, VHDL, even the C programming language and other languages are now used to convert an algorithm into a circuit.
- PC World Review (http://www.pcworld.com/reviews/article/0,aid,104975,src,ov,00.asp)
- IT World review (http://www.itworld.com/Comp/1982/030924nano/)
- AMD (http://investor.com.com/AMD+enters+the+90-nanometer+zone/2100-1006_3-5313410.html)
- Fujitsu (http://www.keepmedia.com/pubs/ECN/2002/08/01/239576?extID=10032&oliID=213)
- Intel (http://www.intel.com/research/silicon/nanometer.htm?iid=labs+research/silicon/nanometer.htm&)
- August, 2002 release by Intel (http://www.intel.com/pressroom/archive/releases/20020813tech.htm)